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| rev. 7524b?mp3?05/06 features ? mpeg i/ii-layer 3 hardwired decoder ? stand-alone mp3 decoder ? 48, 44.1, 32, 24, 22.05, 16 khz sampling frequency ? separated digital volume control on left and right channels (software control using 31 steps) ? bass, medium, and treble control (31 steps) ? bass boost sound effect ? ancillary data extraction ? crc error and mpeg frame synchronization indicators ? 20-bit stereo audio dac ? 93 db snr playback stereo channel ? 32 ohm/ 20 mw stereo headset drivers ? stereo line level input, differential mono auxiliary input ? programmable audio output for interfacing with external audio system ?i 2 s format compatible ? mono audio power amplifier ? 440mw on 8 ohms load ? usb rev 1.1 controller ? full speed data transmission ? built-in pll ? mp3 audio clocks ?usb clock ? multimediacard ? interface, secure digital card interface ? standard full duplex uart with baud rate generator ? power management ? power-on reset ? idle mode, power-down mode ? operating conditions: ? 2.7 to 3v, 10%, 25 ma typical operating at 25c ? 37 ma typical operating at 25c playing music on earphone ? temperature range: -40 c to +85 c ? power amplifier supply 3.2v to 5.5v ? packages ? ctbga 100-pin typical applications ?mp3-player ? pda, camera, mobile phone mp3 ? car audio/multimedia mp3 ? home audio/multimedia mp3 ?toys ? industrial background music / ads single-chip mp3 decoder with full audio interface at83snd2cmp3 at83snd2cdvx preliminary
2 at83snd2cmp3 7524b?mp3?05/06 description the at83snd2cmp3 has been developped as a versatile remote controlled mp3 player for very fast mp3 feature implementation into most existing system. it perfectly fits features needed in mobile phones and toys, but can also be used in any portable equipment and in industrial applications. audio files and any other data can be stored in a nand flash memory or in a removable flash card such as multimediacard (mmc) or secure digital card (sd). music collec- tions are very easy to build, as data can be stored using the standard fat12/16 and fat32 file system. thanks to the usb port, data can be transferred and maintained from and to any com- puter based on windows ? , linux ? and mac os ? . file system is controlled by the at83snd2cmp3 so the host controller does not have to handle it. in addition to the usb device port, the mp3 audio system can be connected to any embedded host through a low cost serial link uart. host controller can fully remote control the mp3 decoder behaviour using a command protocol over the serial link. file system is controlled by the at83snd2cmp3 so host controller does not have to handle it. files can also be uploaded or dowloaded from host environment to nand flash or flash card. 3 at83snd2cmp3 7524b?mp3?05/06 1. block diagram figure 2. block diagram clock and pll unit control unit interrupt handler unit filt x2 x1 mp3 sd / mmc interface i/oports mdat p0-p4 vss vdd keyboard interface kin0 i 2 s/pcm audio int0 int1 3 alternate function of port 3 4 alternate function of port 4 timers 0/1 t1 t0 mclk mcmd rst dsel dclk sclk dout usb controller d+ d- uart rxd txd watchdog uvss uvdd and brg 3 3 3 3 3 audio decoder interface pa audio dac unit hsr hsl auxp 3 auxn linel liner monop monon painp painn hpp hpn x1 x2 4 at83snd2cmp3 7524b?mp3?05/06 pin description pinouts figure 3. at83snd2cmp3 100-pin bga package 1. nc = do not connect auxn 8 9765432 c b a d e f g h 1 nc nc audvdd hsvdd hsvss audvss audvcm nc hsl hsr pvss ingnd d+ p0.0/ nc pvdd linel x2 d- nc p0.3/ nc audvref filt liner x1 vss vss monon p0.4/ p0.5/ vss p3.0/ tst p3.6/ vdd p4.2/ p0.6/ p0.7/ vdd p3.1/ p3.4/ p3.5/ p3.7/ p4.1/ p4.0/ p4.3/ nc esdvss p3.2/ dsel dclk lphn p2.0/ p2.1/ p2.5/ mclk vdd nc sclk dout cbp nc p2.2/ p2.3/ p2.7/ vss mdat audrst vss audvss j p0.2/ p0.1/ nc auxp monop ad7 wr nc vdd p2.4/ p2.6/ nc mcmd rst nc vdd uvss uvdd vdd p3.3/ audvss hpn audvbat hpp painn painp k a8 kin0 ad0 ad4 ad3 ad2 ad1 scl sda ad5 a9 a10 a11 a12 a13 a14 a15 t0 t1 txd rxd rd int1 int0 10 ad6 nc 5 at83snd2cmp3 7524b?mp3?05/06 signals all the at83snd2cmp3 signals are detailed by functionality in following tables. table 1. ports signal description table 2. clock signal description table 3. timer 0 and timer 1 signal description signal name type description alternate function p0.7:0 i/o port 0 p0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high impedance inputs. to avoid any parasitic current consumption, floating p0 inputs must be polarized to v dd or v ss . ad7:0 p2.7:0 i/o port 2 p2 is an 8-bit bidirectional i/o port with internal pull-ups. a15:8 p3.7:0 i/o port 3 p3 is an 8-bit bidirectional i/o port with internal pull-ups. rxd txd int0 int1 t0 t1 wr rd p4.3:0 i/o port 4 p4 is an 8-bit bidirectional i/o port with internal pull-ups. signal name type description alternate function x1 i input to the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. x1 is the clock source for internal timing. - x2 o output of the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, leave x2 unconnected. - filt i pll low pass filter input filt receives the rc network of the pll low pass filter. - signal name type description alternate function int0 i timer 0 gate input int0 serves as external run control for timer 0, when selected by gate0 bit in tcon register. external interrupt 0 int0 input sets ie0 in the tcon register. if bit it0 in this register is set, bit ie0 is set by a falling edge on int0#. if bit it0 is cleared, bit ie0 is set by a low level on int0#. p3.2 6 at83snd2cmp3 7524b?mp3?05/06 table 4. audio interface signal description table 5. usb controller signal description table 6. mutimediacard interface signal description int1 i timer 1 gate input int1 serves as external run control for timer 1, when selected by gate1 bit in tcon register. external interrupt 1 int1 input sets ie1 in the tcon register. if bit it1 in this register is set, bit ie1 is set by a falling edge on int1#. if bit it1 is cleared, bit ie1 is set by a low level on int1#. p3.3 t0 i timer 0 external clock input when timer 0 operates as a counter, a falling edge on the t0 pin increments the count. p3.4 t1 i timer 1 external clock input when timer 1 operates as a counter, a falling edge on the t1 pin increments the count. p3.5 signal name type description alternate function dclk o dac data bit clock - dout o dac audio data output - dsel o dac channel select signal dsel is the sample rate clock output. - sclk o dac system clock sclk is the oversampling clock synchronized to the digital audio data (dout) and the channel selection signal (dsel). - signal name type description alternate function d+ i/o usb positive data upstream port this pin requires an external 1.5 k pull-up to v dd for full speed operation. - d- i/o usb negative data upstream port - signal name type description alternate function mclk o mmc clock output data or command clock transfer. - mcmd i/o mmc command line bidirectional command channel used for card initialization and data transfer commands. to avoid any parasitic current consumption, unused mcmd input must be polarized to v dd or v ss . - mdat i/o mmc data line bidirectional data channel. to avoid any parasitic current consumption, unused mdat input must be polarized to v dd or v ss . - signal name type description alternate function 7 at83snd2cmp3 7524b?mp3?05/06 table 7. uart signal description table 8. keypad interface signal description table 9. system signal description table 10. power signal description signal name type description alternate function rxd i/o receive serial data rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2 and 3. p3.0 txd o transmit serial data txd outputs the shift clock in serial i/o mode 0 and transmits data in serial i/o modes 1, 2 and 3. p3.1 signal name type description alternate function kin0 i keypad input line holding this pin high or low for 24 oscillator periods triggers a keypad interrupt. - signal name type description alternate function rst i reset input holding this pin high for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage lower than v il is applied, whether or not the oscillator is running. this pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and v dd . asserting rst when the chip is in idle mode or power-down mode returns the chip to normal operation. - tst i test input test mode entry signal. this pin must be set to v dd . - signal name type description alternate function vdd pwr digital supply voltage connect these pins to +3v supply voltage. - vss gnd circuit ground connect these pins to ground. - pvdd pwr pll supply voltage connect this pin to +3v supply voltage. - pvss gnd pll circuit ground connect this pin to ground. - uvdd pwr usb supply voltage connect this pin to +3v supply voltage. - 8 at83snd2cmp3 7524b?mp3?05/06 table 11. audio power signal description table 12. stereo audio dac and mono power amplifier signal description uvss gnd usb ground connect this pin to ground. - signal name type description alternate function audvdd pwr audio digital supply voltage - audvss gnd audio circuit ground connect these pins to ground. - esdvss gnd audio analog circuit ground for electrostatic discharge . connect this pin to ground. - audvref pwr audio voltage reference pin for decoupling .- hsvdd pwr headset driver power supply .- hsvss gnd headset driver ground. connect this pin to ground. - audvbat pwr audio amplifier supply. - signal name type description alternate function lphn o low power audio stage output - hpn o negative speaker output - hpp o positivie speaker output - cbp o audio amplifier common mode voltage decoupling - painn i audio amplifier negative input - painp i audio amplifier positive input - audrst i audio reset (active low) - monon o audio negative monaural driver output - monop o audio positive monaural driver outpu t- auxp i audio mono auxiliary positive input - auxn i audio mono auxiliary negative input - hsl o audio left channel headset driver output - hsr o audio right channel headset driver output - linel i audio left channel line in - liner i audio right channel line in - ingnd i audio line signal ground pin for decoupling .- audvcm i audio common mode reference for decoupling - signal name type description alternate function 9 at83snd2cmp3 7524b?mp3?05/06 internal pin structure table 13. detailed internal pin structure notes: 1. for information on resistors value, input/output levels, and drive capability, refer to the dc characteristics. 2. when the two wire controller is enabled, p 3 transistors are disabled allowing pseudo open-drain structure. circuit (1) type pins input tst input/output rst input/output p3 p4 input/output p0 mcmd mdat output ale sclk dclk dout dsel mclk input/output d+ d- r tst vdd r rst vss p vdd watchdog output p 3 vss n p 1 vdd vdd 2 osc latch output periods p 2 vdd vss n p vdd vss n p vdd d+ d- 10 at83snd2cmp3 7524b?mp3?05/06 clock controller the clock controller is based on an on-chip oscillator feeding an on-chip phase lock loop (pll). all internal clocks to the peripherals and cpu core are generated by this controller. oscillator the x1 and x2 pins are the input and the output of a single-stage on-chip inverter (see figure 4) that can be configured with off-chip components such as a pierce oscillator (see figure 5). value of capacitors and crystal characteristics are detailed in the section ?dc characteristics?. the oscillator outputs three different clocks: a clock for the pll, a clock for the cpu core, and a clock for the peripherals as shown in figure 4. these clocks are either enabled or disabled, depending on the power reduction mode as detailed in the section. the peripheral clock is used to generate the timer 0, timer 1, mmc, spi, and port sam- pling clocks. figure 4. oscillator block diagram and symbol figure 5. crystal connection pll pll description the pll is used to generate internal high frequency clock (the pll clock) synchronized with an external low-frequency (the oscillator clock). the pll clock provides the mp3 decoder, the audio interface, and the usb inte rface clocks. figure 6 shows the internal structure of the pll. the pfld block is the phase frequency comparator and lock detector. this block makes the comparison between the reference clock coming from the n divider and the reverse clock coming from the r divider and generates some pulses on the up or down signal depending on the edge position of the reverse clock. the pllen bit in pllcon register is used to enable the clock generation. the chp block is the charge pump that generates the voltage reference for the vco by injecting or extracting charges from the external filter connected on pfilt pin (see x1 x2 pd pcon.1 idl pcon.0 peripheral cpu core 0 1 x2 ckcon.0 2 per clock clock clock peripheral clock symbol cpu clock cpu core clock symbol osc clock oscillator clock symbol oscillator clock vss x1 x2 q c1 c2 11 at83snd2cmp3 7524b?mp3?05/06 figure 7). value of the filter components are detailed in the section ?dc characteristics?. the vco block is the voltage controlled oscillator controlled by the voltage v ref pro- duced by the charge pump. it generates a square wave signal: the pll clock. figure 6. pll block diagram and symbol figure 7. pll filter connection pll programming the pll is programmed using the flow shown in figure 8. the pll clock frequency will depend on mp3 decoder clock and audio interface clock frequencies. figure 8. pll programming flow pllen pllcon.1 n6:0 n divider r divider vco pllclk oscclk r 1 + () n1 + ---------------------------------------------- - = osc clock pfld plock pllcon.0 pfilt chp vref up down r9:0 pll clock pll clock symbol pll cloc k vss filt r c1 c2 vss pll programming configure dividers n6:0 = xxxxxxb r9:0 = xxxxxxxxxxb enable pll pllres = 0 pllen = 1 pll locked? plock = 1? 12 at83snd2cmp3 7524b?mp3?05/06 mp3 decoder the product implements a mpeg i/ii audio layer 3 decoder better known as mp3 decoder. in mpeg i (iso 11172-3) three layers of compression have been standardized support- ing three sampling frequencies: 48, 44.1, and 32 khz. among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining cd audio quality. for example, 3 minutes of cd audio (16-bit pcm, 44.1 khz) data, which needs about 32m bytes of storage, can be encoded into only 2.7m bytes of mpeg i audio layer 3 data. in mpeg ii (iso 13818-3), three additional sampling frequencies: 24, 22.05, and 16 khz are supported for low bit rates applications. the at83snd2cmp3 can decode in real-time the mpeg i audio layer 3 encoded data into a pcm audio data, and also supports mpeg ii audio layer 3 additional frequencies. additional features are supported by the at83snd2cmp3 mp3 decoder such as vol- ume control, bass, medium, and treble controls, bass boost effect and ancillary data extraction. decoder description the core interfaces to the mp3 decoder through nine special function registers: mp3con, the mp3 control register; mp3sta, the mp3 status register; mp3dat, the mp3 data register; mp3anc, the ancillary data register; mp3vol and mp3vor, the mp3 volume left and right control registers; mp3bas, mp3med, and mp3tre, the mp3 bass, medium, and treble control registers; and mpclk, the mp3 clock divider register. figure 9 shows the mp3 decoder block diagram. figure 9. mp3 decoder block diagram mpen mp3con.7 mp3 clock audio data from c51 1k bytes 8 mpxreq mp3sta1.n header checker stereo processor huffman decoder imdct side information errxxx mp3sta.5:3 16 sub-band synthesis decoded data to audio interfac e anti-aliasing mpfs1:0 mp3sta.2:1 dequantizer mpver mp3sta.0 mpbbst mp3con.6 mp3vol mp3vor mp3bas mp3med mp3tre ancillary buffer mp3anc frame buffer mp3dat 13 at83snd2cmp3 7524b?mp3?05/06 mp3 data the mp3 decoder does not start any frame decoding before having a complete frame in its input buffer (1) . in order to manage the load of mp3 data in the frame buffer, a hard- ware handshake consisting of data request and data acknowledgment is implemented. each time the mp3 decoder needs mp3 data, it sets the mpreq, mpfreq and mpbreq flags respectively in mp3sta and mp3sta1 registers. mpreq flag can gen- erate an interrupt if enabled as explained in section ?interrupt?. the cpu must then load data in the buffer by writing it through mp3dat register thus acknowledging the previ- ous request. as shown in figure 10, the mpfreq flag remains set while data (i.e a frame) is requested by the decoder. it is cleared when no more data is requested and set again when new data are requested. mpbreq flag toggles at every byte writing. note: 1. the first request after enable, consists in 1024 bytes of data to fill in the input buffer. figure 10. data timing diagram mp3 clock the mp3 decoder clock is generated by division of the pll clock. the division factor is given by mpcd4:0 bits in mp3clk register. figure 11 shows the mp3 decoder clock generator and its calculation formula. the mp3 decoder clock frequency depends only on the incoming mp3 frames. figure 11. mp3 clock generator and symbol as soon as the frame header has been decoded and the mpeg version extracted, the minimum mp3 input frequency must be programmed according to table 14. table 14. mp3 clock frequency mpfreq flag mpbreq flag mpreq flag cleared when reading mp3sta write to mp3dat mpeg version minimum mp3 clock (mhz) i21 ii 10.5 mpcd4:0 mp3clk mp3 decoder clock mp3clk pllclk mpcd 1 + ---------------------------- = mp3 clock mp3 clock symbol pll clock 14 at83snd2cmp3 7524b?mp3?05/06 audio controls volume control the mp3 decoder implements volume control on both right and left channels. the mp3vor and mp3vol registers allow a 32-step volume control according to table 15. table 15. volume control equalization control sound can be adjusted using a 3-band equalizer: a bass band under 750 hz, a medium band from 750 hz to 3300 hz and a treble band over 3300 hz. the mp3bas, mp3med, and mp3tre registers allow a 32-step gain control in each band according to table 16. table 16. bass, medium, treble control vol4:0 or vor4:0 volume gain (db) 00000 mute 00001 -33 00010 -27 11110 -1.5 11111 0 bas4:0 or med4:0 or tre4:0 gain (db) 00000 - 00001 -14 00010 -10 11110 +1 11111 +1.5 15 at83snd2cmp3 7524b?mp3?05/06 frame information the mp3 frame header contains information on the audio data contained in the frame. these informations is made available in the mp3sta register for you information. mpver and mpfs1:0 bits allow decoding of the sampling frequency according to table 17. mpver bit gives the mpeg version (2 or 1). table 17. mp3 frame frequency sampling ancillary data mp3 frames also contain data bits called ancillary data. these data are made available in the mp3anc register for each frame. as shown in figure 12, the ancillary data are available by bytes when mpanc flag in mp3sta register is set. mpanc flag is set when the anc illary buffer is not empty (at least one ancillary data is available) and is cleared only when there is no more ancillary data in the buffer. this flag can generate an interrupt as explained in section ?interrupt?. when set, software must read all bytes to empty the ancillary buffer. figure 12. ancillary data block diagram mpver mpfs1 mpfs0 fs (khz) 0 0 0 22.05 (mpeg ii) 0 0 1 24 (mpeg ii) 0 1 0 16 (mpeg ii) 011reserved 1 0 0 44.1 (mpeg i) 10148 (mpeg i) 11032 (mpeg i) 111reserved ancillary data to c51 8 mp3anc 8 mpanc mp3sta.7 7-byte ancillary buffer 16 at83snd2cmp3 7524b?mp3?05/06 audio output interface the product implements an audio output interface allowing the audio bitstream to be output in various formats. it is compatible with right and left justification pcm and i 2 s for- mats and thanks to the on-chip pll (see section ?clock controller?, page 10) allows connection of almost all of the commercial audio dac families available on the market. the audio bitstream can be from 2 different types: ? the mp3 decoded bitstream coming from the mp3 decoder for playing songs. ? the audio bitstream coming from the mcu for outputting voice or sounds. description the control unit core interfaces to the audio interface through five special function regis- ters: audcon0 and audcon1, the audio control registers ; audsta, the audio status register; auddat, the audio data register; and audclk, the audio clock divider register. figure 13 shows the audio interface block diagram, blocks are detailed in the following sections. figure 13. audio interface block diagram aud clock udrn audsta.6 0 1 dsiz audcon0.1 dsel clock generator dclk dou t sclk just4:0 audcon0.7:3 pol audcon0.2 auden audcon1.0 hlr audcon0.0 0 1 src audcon1.7 8 data converter audio data from c51 audio data from mp3 dup1:0 audcon1.2:1 16 16 sreq audsta.7 audio buffer aubusy audsta.5 data ready drqen audcon1.6 mp3 buffer decoder 16 sample request to mp3 decoder auddat 17 at83snd2cmp3 7524b?mp3?05/06 clock generator the audio interface clock is generated by division of the pll clock. the division factor is given by aucd4:0 bits in clkaud register. figure 14 shows the audio interface clock generator and its calculation formula. the audio interface clock frequency depends on the incoming mp3 frames and the audio dac used. figure 14. audio clock generator and symbol as soon as audio interface is enabled by setting auden bit in audcon1 register, the master clock generated by the pll is output on the sclk pin which is the dac system clock. this clock is output at 256 or 384 times the sampling frequency depending on the dac capabilities. hlr bit in audcon0 register must be set according to this rate for properly generating the audio bit clock on the dclk pin and the word selection clock on the dsel pin. these clocks are not generated when no data is available at the data converter input. for dac compatibility, the bit clock frequency is programmable for outputting 16 bits or 32 bits per channel using the dsiz bit in audcon0 register (see section "data con- verter", page 17), and the word selection signal is programmable for outputting left channel on low or high level according to pol bit in audcon0 register as shown in figure 15. figure 15. dsel output polarity data converter the data converter block converts the audio stream input from the 16-bit parallel format to a serial format. for accepting all pcm formats and i 2 s format, just4:0 bits in audcon0 register are used to shift the data output point. as shown in figure 16, these bits allow msb justification by setting just4:0 = 00000, lsb justification by setting just4:0 = 10000, i 2 s justification by setting just4:0 = 00001, and more than 16-bit lsb justification by filling the low significant bits with logic 0. aucd4:0 audclk audio interface clock audclk pllclk au c d1 + --------------------------- = audio clock symbol aud clock pll clock left channel right channel pol = 1 pol = 0 left channel right channel 18 at83snd2cmp3 7524b?mp3?05/06 figure 16. audio output format the data converter receives its audio stream from 2 sources selected by the src bit in audcon1 register. when cleared, the audio stream comes from the mp3 decoder (see section ?mp3 decoder?, page 12) for song playing. when set, the audio stream is com- ing from the c51 core for voice or sound playing. as soon as first audio data is input to the data converter, it enables the clock generator for generating the bit and word clocks. audio buffer in voice or sound playing mode, the audio stream comes from the c51 core through an audio buffer. the data is in 8-bit format and is sampled at 8 khz. the audio buffer adapts the sample format and rate. the sample format is extended to 16 bits by filling the lsb to 00h. rate is adapted to the dac rate by duplicating the data using dup1:0 bits in audcon1 register according to table 18. the audio buffer interfaces to the c51 core through three flags: the sample request flag (sreq in audsta register), the under-run flag (undr in audsta register) and the busy flag (aubusy in audsta register). sreq and undr can generate an interrupt request as explained in section "interrupt request", page 19. the buffer size is 8 bytes large. sreq is set when the samples number switches from 4 to 3 and reset when the samples number switches from 4 to 5; u ndr is set when the buffer becomes empty sig- naling that the audio interface ran out of samples; and aubusy is set when the buffer is full. dsel dclk dout msb i 2 s format with dsiz = 0 and just4:0 = 00001. lsb b14 msb lsb b14 b1 b1 dsel dclk dout msb i 2 s format with dsiz = 1 and just4:0 = 00001. lsb b14 msb lsb b14 1 2 3 13141516 1 2 3 13141516 left channel right channel 123 1718 32 123 1718 32 dsel dclk dout b14 msb/lsb justified format with dsiz = 0 and just4:0 = 00000. msb b1 b15 msb b1 lsb lsb 1 2 3 13141516 1 2 3 13141516 left channel right channel left channel right channel dsel dclk dout 16-bit lsb justified format with dsiz = 1 and just4:0 = 10000. 11618 32 32 left channel right channel 17 31 msb b14 lsb b1 msb b14 lsb b1 11618 17 31 dsel dclk dout 18-bit lsb justified format with dsiz = 1 and just4:0 = 01110. 115 3032 left channel right channel 16 31 msb b16 b2 1 b1 lsb msb b16 b2 b1 lsb 15 30 32 16 31 19 at83snd2cmp3 7524b?mp3?05/06 table 18. sample duplication factor mp3 buffer in song playing mode, the audio stream comes from the mp3 decoder through a buffer. the mp3 buffer is used to store the decoded mp3 data and interfaces to the decoder through a 16-bit data input and data request signal. this signal asks for data when the buffer has enough space to receive new data. data request is conditioned by the dreqen bit in audcon1 register. when set, the buffer requests data to the mp3 decoder. when cleared no more data is requested but data are output until the buffer is empty. this bit can be used to suspend the audio generation (pause mode). interrupt request the audio interrupt request can be generated by 2 sources when in c51 audio mode: a sample request when sreq flag in audsta register is set to logic 1, and an under-run condition when udrn flag in audsta register is set to logic 1. both sources can be enabled separately by masking one of them using the msreq and mudrn bits in audcon1 register. a global enable of the audio interface is provided by setting the eaud bit in ien0 register. the interrupt is requested each time one of the 2 sources is set to one. the source flags are cleared by writing some data in the audio buffer through auddat, but the global audio interrupt flag is cleared by hardwar e when the interrupt service routine is executed. figure 17. audio interface interrupt system mp3 song playing in mp3 song playing mode, the operations to do are to configure the pll and the audio interface according to the dac selected. the audio clock is programmed to generate the 256fs or 384fs as explained in section "clock generator", page 17. figure 18 shows the configuration flow of the audio interface when in mp3 song mode. dup1 dup0 factor 0 0 no sample duplication, dac rate = 8 khz (c51 rate). 0 1 one sample duplication, dac rate = 16 khz (2 x c51 rate). 1 0 2 samples duplication, dac rate = 32 khz (4 x c51 rate). 1 1 three samples duplication, dac rate = 48 khz (6 x c51 rate). sreq audsta.7 audio interrup t reques t udrn audsta.6 msreq audcon1.5 eaud ien0.6 mudrn audcon1.4 20 at83snd2cmp3 7524b?mp3?05/06 figure 18. mp3 mode audio configuration flow mp3 mode configuration configure interface hlr = x dsiz = x pol = x just4:0 = xxxxxb src = 0 program audio clock enable dac system clock auden = 1 wait for dac set-up time enable data request drqen = 1 21 at83snd2cmp3 7524b?mp3?05/06 dac and pa interface the at83snd2cmp3 implements a stereo audio digital-to-analog converter and audio power amplifier targeted for li-ion or ni-mh battery powered devices. figure 19. audio interface block diagram dac the stereo dac section is a complete high performance, stereo, audio digital-to-analog converter delivering 93 db dynamic range. it comprises a multibit sigma-delta modula- tor with dither, continuous time analog filters and analog output drive circuitry. this architecture provides a high insensitivity to clock jitter. the digital interpolation filter increases the sample rate by a factor of 8 using 3 linear phase half-band filters cas- caded, followed by a first order sinc interpolator with a factor of 8. this filter eliminates the images of baseband audio, remaining only the image at 64x the input sample rate, which is eliminated by the analog post filter. optionally, a dither signal can be added that may reduce eventual noise tones at the output. however, the use of a multibit sigma- delta modulator already provides extremely low noise tones energy. master clock is 128 up to 512 times the input data rate allowing choice of input data rate up to 50 khz, including standard audio rates of 48, 44.1, 32, 16 and 8 khz. the dac section is followed by a volume and mute control and can be simultaneously played back directly through a stereo 32 headset pair of drivers. the stereo 32 headset pair of drivers also includes a mixer of a linel and liner pair of stereo inputs as well as a differential monaural auxiliary input (line level). mp3 i 2 s/pcm audio dsel dclk sclk dout audio decoder interface pa audio dac unit hsr hsl auxp auxn linel liner monop monon painp painn hpp hpn audcdin audcclk audccs serial audio interface audcdout 22 at83snd2cmp3 7524b?mp3?05/06 dac features ? 20 bit d/a conversion ? 72db dynamic range, -75db thd stereo line-in or microphone interface with 20db amplification ? 93db dynamic range, -80db thd stereo d/a conversion ? 74db dynamic range / -65db thd for 20mw output power over 32 ohm loads ? stereo, mono and reverse stereo mixer ? left/right speaker short-circuit detection flag ? differential mono auxiliary input amplifier and pa driver ? audio sampling rates (fs): 16, 22.05, 24, 32, 44.1 and 48 khz. figure 20. stereo dac functional diagram digital signals timing data interface to avoid noises at the output, the reset state is maintained until proper synchronism is achieved in the dac serial interface: ?dsel ?sclk ? dclk ?dout the data interface allows three different data transfer modes: digital filter digital filter volume control volume control volume control volume control spkr drv 32 dac dac pga pga spkr drv 32 hsr hsl linel liner serial to parallel interface dsel dclk + + auxn auxp aux padrv monon monop + + + dout sclk dac_olc gain 6 to -6db (3db) llig,rlig gain 20,12 to -33 db (3db) auxg gain pa gain line out gain llog, rlog 0 to -46.5db (1.5db) master playback gain 12 to -34db (1.5db) 23 at83snd2cmp3 7524b?mp3?05/06 figure 21. 20 bit i2s justified mode figure 22. 20 bit msb justified mode figure 23. 20 bit lsb justified mode the selection between modes is done using the dintsel 1:0 in dac_misc register (table 40.) according with the following table: the data interface always works in slave mode. this means that the dsel and the dclk signals are provided by microcontroller audio data interface. serial audio dac interface the serial audio dac interface is a synchronous peripheral interface (spi) in slave mode: ? audcdin: is used to transfer data in series from the master to the slave dac. it is driven by the master. ? audcdout: is used to transfer data in series from the slave dac to the master. it is driven by the selected slave dac. ? serial clock (audcclk): it is used to synchronize the data transmission both in and out the devices through the audcdin and audcdout lines. note: refer to table 29. for dac spi interface description r1 r0 l(n-1) l(n-2) l(n-3) ... l2 l1 l0 r(n-1) r(n-2) r(n-3) ... r2 r1 r0 sclk dsel dout r0 l(n-1) l(n-2) l(n-3) ... l2 l1 l0 r(n-1) r(n-2) r(n-3) ... r2 r1 r0 l(n-1) sclk dsel dout r0 l(n-1) l(n-2) ... l1 l0 r(n-1) r(n-2) ... r1 r0 l(n-1) sclk dsel dout dintsel 1:0 format 00 i2s justified 01 msb justified 1x lsb justified 24 at83snd2cmp3 7524b?mp3?05/06 figure 24. serial audio interface protocol is as following to access dac registers: figure 25. dac spi interface dac interface spi protocol on audcdin, the first bit is a read/write bit. 0 indicates a write operation while 1 is for a read operation. the 7 following bits are used for the register address and the 8 last ones are the write data. for both address and data, the most significant bit is the first one. in case of a read operation, audcdout prov ides the contents of the read register, msb first. the transfer is enabled by the audccs signal active low. the interface is resetted at every rising edge of audccs in order to come back to an idle state, even if the transfer does not succeed. the dac interface spi is synchronized with the serial clock audc- audio pa audio dac audcdin audcclk audccs serial audio interface audcdout rw 6 d d6 d5 d3 d7 d6 d d4 d1 d0 d2 d3 d0 d1 d2 d4 a0 audcdout audcdin audcclk audccs 25 at83snd2cmp3 7524b?mp3?05/06 clk. falling edge latches audcdin input and rising edge shifts audcdout output bits. note that the dlck must run during any dac spi interface access (read or write). figure 26. dac spi interface timings table 19. dac spi interface timings thsdi tc tssdi audcdout audcdin audcclk tdsdo audccs timing parameter description min max tc audcclk min period 150 ns - twl audcclk min pulse width low 50 ns - twh audcclk min pulse width high 50 ns - tssen setup time audccs falling to audcclk rising 50 ns - thsen hold time audcclk falling to audccs rising 50 ns - tssdi setup time audcdin valid to audcclk falling 20 ns - thsdi hold time audcclk falling to audcdin not valid 20 ns - tdsdo delay time audcclk rising to audcdout valid - 20 ns thsdo hold time audcclk rising to audcdout not valid 0 ns - 26 at83snd2cmp3 7524b?mp3?05/06 dac register tables table 20. dac register address dac gain the dac implements severals gain control: line-in (table 21.), master playback (), line- out (table 24.). address register name access reset state 00h dac_ctrl dac control read/write 00h 01h dac_llig dac left line in gain read/write 05h 02h dac_rlig dac right line in gain read/write 05h 03h dac_lpmg dac left master playback gain read/write 08h 04h dac_rpmg dac right master playback gain read/write 08h 05h dac_llog dac left line out gain read/write 00h 06h dac_rlog dac right line out gain read/write 00h 07h dac_olc dac output level control read/write 22h 08h dac_mc dac mixer control read/write 09h 09h dac_csfc dac clock and sampling frequency control read/write 00h 0ah dac_misc dac miscellaneous read/write 00h 0ch dac_prech dac precharge control read/write 00h 0dh dac_auxg dac auxilary input gain control read/write 05h 10h dac_rst dac reset read/write 00h 11h pa_crtl power amplifier control read/write 00h table 21. line-in gain llig 4:0 rlig 4:0 gain (db) 00000 20 00001 12 00010 9 00011 6 00100 3 00101 0 00110 -3 00111 -6 01000 -9 01001 -12 01010 -15 01011 -18 01100 -21 27 at83snd2cmp3 7524b?mp3?05/06 01101 -24 01110 -27 01111 -30 10000 -33 10001 < -60 table 22. master playback gain lmpg 5:0 rmpg 5:0 gain (db) 000000 12.0 000001 10.5 000010 9.0 000011 7.5 000100 6.0 000101 4.5 000110 3.0 000111 1.5 001000 0.0 001001 -1.5 001010 -3.0 001011 -4.5 001100 -6.0 001101 -7.5 001110 -9.0 001111 -10.5 010000 -12.0 010001 -13.5 010010 -15.0 010011 -16.5 010100 -18.0 010101 -19.5 010110 -21.0 010111 -22.5 011000 -24.0 011001 -25.5 table 21. line-in gain (continued) 28 at83snd2cmp3 7524b?mp3?05/06 011010 -27.0 011011 -28.5 011100 -30.0 011101 -31.5 011110 -33.0 011111 -34.5 100000 mute table 23. line-out gain llog 5:0 rlog 5:0 gain (db) 000000 0.0 000001 -1.5 000010 -3.0 000011 -4.5 000100 -6.0 000101 -7.5 000110 -9.0 000111 -10.5 001000 -12.0 001001 -13.5 001010 -15.0 001011 -16.5 001100 -18.0 001101 -19.5 001110 -21.0 001111 -22.5 010000 -24.0 010001 -25.5 010010 -27.0 010011 -28.5 010100 -30.0 010101 -31.5 010110 -33.0 table 22. master playback gain (continued) lmpg 5:0 rmpg 5:0 gain (db) 29 at83snd2cmp3 7524b?mp3?05/06 table 24. dac output level control digital mixer control the audio dac features a digital mixer that allows the mixing and selection of multiple input sources. the mixing / multiplexing functions are described in the following table according with the next figure: figure 27. mixing / multiplexing functions note: whenever the two mixer inputs are selected, a ?6 db gain is applied to the output signal. whenever only one input is selected, no gain is applied. 010111 -34.5 011000 -36.0 011001 -37.5 011010 -39.0 011011 -40.5 011100 -42.0 011101 -43.5 011110 -45.0 011111 -46.5 100000 mute lolc 2:0 rolc 2:0 gain (db) 000 6 001 3 010 0 011 -3 100 -6 table 23. line-out gain (continued) volume control volume control volume control volume control + + 1 2 2 1 left channel right channel from digital filters to dacs 30 at83snd2cmp3 7524b?mp3?05/06 note: refer to dac_mc register table 38. for signal description master clock and sampling frequency selection the following table describes the different modes available for master clock and sam- pling frequency selection by setting ovrsel bit in dac_csfc register (refer to table 39.). table 25. master clock selection the selection of input sample size is done using the nbits 1:0 in dac_misc register (refer to table 40.) according to table 26. table 26. input sample size selection the selection between modes is done using dintsel 1:0 in dac_misc register (refer to table 40.) according to table 27. table 27. format selection de-emphasis and dither enable the circuit features a de-emphasis filter for the playback channel. to enable the de- emphasis filtering, deempen must be set to high. likewise, the dither option (added in the playback channel) is enabled by setting the dithen signal to high. signal description lmsmin1 left channel mono/stereo mixer left mixed input enable ? high to enable, low to disable lmsmin2 left channel mono/stereo mixer right mixed input enable ? high to enable, low to disable rmsmin1 right channel mono/stereo mixer left mixed input enable ? high to enable, low to disable rmsmin2 right channel mono/stereo mixer right mixed input enable ? high to enable, low to disable ovrsel master clock 0256 x fs 1384 x fs nbits 1:0 format 00 16 bits 01 18 bits 10 20 bits dintsel 1:0 format 00 i2s justified 01 msb justified 1x lsb justified 31 at83snd2cmp3 7524b?mp3?05/06 table 28. dac auxlilary input gain auxg 4:0 gain (db) 00000 20 00001 12 00010 9 00011 6 00100 3 00101 0 00110 -3 00111 -6 01000 -9 01001 -12 01010 -15 01011 -18 01100 -21 01101 -24 01110 -27 01111 - 30 10000 -33 10001 <-60 32 at83snd2cmp3 7524b?mp3?05/06 register table 29. auxcon register auxcon (s:90h) ? auxiliary control register reset value = 1111 1111b 76 5 4 3 2 1 0 sda scl - audcdout audcdin audcclk audccs kin0 bit number bit mnemonic description 7sda twi serial data sda is the bidirectional two wire data line. 6scl twi serial clock when twi controller is in master mode, scl outputs the serial clock to the slave peripherals. when twi controller is in slave mode, scl receives clock from the master controller. 5 - not used. 4 audcdout audio dac spi data output . 3 audcdin audio dac spi data input 2 audcclk audio dac spi clock 1 audccs audio dac chip select set to deselect dac clear to select dac 0kin0 keyboard input interrupt . 33 at83snd2cmp3 7524b?mp3?05/06 table 30. dac control register register - dac_ctrl (00h) reset value = 00000000b table 31. dac left line in gain register - dac_llig (01h) reset value = 00000101b 76543210 onpadrv onauxin ondacr ondacl onlnor onlnol onlnir onlnil bit number bit mnemonic description 7onpadrv differential mono pa driver clear to power down. set to power up. 6 onauxin differential mono auxiliary input amplifier clear to power down. set to power up. 5 ondacr right channel dac clear to power down. set to power up. 4 ondacl left channel dac clear to power down. set to power up. 3 onlnor right channel line out driver clear to power down. set to power up. 2 onlnol left channel line out driver clear to power down. set to power up. 1 onlnir right channel line in amplifier clear to power down. set to power up. 0 onlnil left channel line in amplifier clear to power down. set to power up. 76543210 - - - llig4 llig3 llig2 llig1 llig0 bit number bit mnemonic description 7:5 - not used 4:0 llig 4:0 left channel line in analog gain selector 34 at83snd2cmp3 7524b?mp3?05/06 table 32. dac right line in gain register - dac_rlig (02h) reset value = 0000101b table 33. dac left master playback gain register - dac_lmpg (03h) reset value = 00001000b table 34. dac right master playback gain register - dac_rmpg (04h) reset value = 00001000b table 35. dac left line out gain register - dac_llog (05h) reset value = 00000000b 76543210 - - - rlig4 rlig3 rlig2 rlig1 rlig0 bit number bit mnemonic description 7:5 - not used 4:0 rlig 4:0 right channel line in analog gain selector 76543210 - - lmpg5 lmpg4 lmpg3 lmpg2 lmpg1 lmpg0 bit number bit mnemonic description 7:6 - not used 5:0 lmpg 5:0 left channel master playback digital gain selector 76543210 - - rmpg5 rmpg4 rmpg3 rmpg2 rmpg1 rmpg0 bit number bit mnemonic description 7:6 - not used 5:0 rmpg 5:0 right channel master playback digital gain selector 76543210 -- llog5 llog4 llog3 llog2 llog1 llog0 bit number bit mnemonic description 7:6 - not used 5:0 llog 5:0 left channel line out digital gain selector 35 at83snd2cmp3 7524b?mp3?05/06 table 36. dac rigth line out gain register - dac_rlog (06h) reset value = 00000000b table 37. dac output level control register - dac_olc (07h) reset value = 00100010b 76543210 - - rlog5 rlog4 rlog3 rlog2 rlog1 rlog0 bit number bit mnemonic description 7:6 - not used 5:0 rlog 5:0 right channel line out digital gain selector 76543210 rshort rolc2 rloc1 rloc0 lshort lolc2 lolc1 lolc0 bit number bit mnemonic description 7rshort right channel short circuit indicator (persistent; after being set, bit is not cleared automatically even after the short circuit is eliminated; must be cleared by reset cycle or direct register write operation) 6:4 rolc 2:0 right channel output level control selector 3lshort left channel short circuit indicator (persistent; after being set, bit is not cleared automatically even after the short circuit is eliminated; must be cleared by reset cycle or direct register write operation) 2:0 lolc 2:0 left channel output level control selector 36 at83snd2cmp3 7524b?mp3?05/06 table 38. dac mixer control register - dac_mc (08h) reset value = 00001001b table 39. dac mixer control register - dac_csfc (09h) reset value = 00000000b 76 5 4 3 2 1 0 - - invr invl rmsmin2 rmsmin1 lmsmin2 lmsmin1 bit number bit mnemonic description 7:6 - not used 5invr right channel mixer output invert set to enable. clear to disable. 4invl left channel mixer output invert. set to enable. clear to disable. 3 rmsmin2 right channel mono/stereo mixer right mixed input enable set to enable. clear to disable. 2 rmsmin1 right channel mono/stereo mixer left mixed input enable set to enable. clear to disable. 1 lmsmin2 left channel mono/stereo mixer right mixed input enable set to enable. clear to disable. 0 lmsmin1 left channel mono/stereo mixer left mixed input enable set to enable. clear to disable. 76543210 -- -ovrsel- - - - bit number bit mnemonic description 7:5 - not used 4ovrsel master clock selector clear for 256 x fs. set for 384 x fs. 3:0 - not used 37 at83snd2cmp3 7524b?mp3?05/06 table 40. dac miscellaneous register - dac_ misc (0ah) reset value = 00000010b table 41. dac precharge control register - dac_ prech (0ch) reset value = 00000000b 76 5 4 3 2 1 0 - - dintsel1 dintsel0 dithen deempen nbits1 nbits0 bit number bit mnemonic description 7 - not used 6 - not used 5:4 dintsel1:0 i2s data format selector 3 dithen dither enable (clear this bit to disable, set to enable) 2 deempen de-emphasis enable (clear this bit to disable, set to enable) 1:0 nbits 1:0 data interface word length 76543210 prchar gepadrv - prchar geauxin - prchar gelnor prchar gelnol prchar gelnil prchar gelnil prchar ge onmstr bit number bit mnemonic description 7 prchargepad rv differential mono pa driver pre-charge. set to charge. 6 prchargeaux in differential mono auxiliary input pre-charge. set to charge. 5 prchargelno r right channel line out pre-charge. set to charge. 4 prchargelno l left channel line out pre-charge. set to charge. 3 prchargelni r right channel line in pre-charge. set to charge. 2 prchargelnil left channel line in pre-charge set to charge. 1 prcharge master pre-charge set to charge. 0onmstr master power on control clear to power down. set to to power up. 38 at83snd2cmp3 7524b?mp3?05/06 table 42. dac auxilary input gain register - dac_ auxg (0dh)l reset value = 0000101b dac reset register - dac_ rst (10h) reset value = 00000000b note: refer to audio dac startup sequence. 76543210 - - - auxg4 auxg3 auxg2 auxg1 auxg0 bit number bit mnemonic description 7:5 - not used 4:0 auxg 4:0 differential mono auxiliary input analog gain selector 76543210 - - - - - resmask resfilz rstz bit number bit mnemonic description 7:3 - not used. 2 resmask active high reset mask of the audio codec 1 resfilz active low reset of the audio codec filter 0rstz active low reset of the audio codec 39 at83snd2cmp3 7524b?mp3?05/06 power amplifier high quality mono output is provided. the dac output is connected through a buffer stage to the input of the audio power amplifier, using two coupling capacitors the mono buffer stage also includes a mixer of the linel and liner inputs as well as a dif- ferential monaural auxiliary input (line level) which can be, for example, the output of a voice codec output driver in mobile phones. in the full power mode, the power amplifier is capable of driving an 8 loudspeaker at maximum power of 440mw, making it suitable as a handsfree speaker driver in wire- less handset application. the low power mode is designed to be switched from the handsfree mode to the nor- mal earphone/speaker mode of a telephone handset. the audio power amplifier is not internally protected against short-circuit. the user should avoid any short-circuit on the load. pa features ? 0.44w on 8 load ? low power mode for earphone ? programmable gain (-22 to +20 db) ? fully differential structure, input and output table 43. pa gain apagain 3:0 gain (db) 0000 -22 0001 20 0010 17 0011 14 0100 11 0101 8 0110 5 0111 2 1000 -1 1001 -4 1010 -7 1011 -10 1100 -13 1101 -16 1110 -19 1111 -22 40 at83snd2cmp3 7524b?mp3?05/06 table 44. pa operating mode table 45. pa low power mode audio supplies and start-up in operating mode audvbat (s upply of the audio power amplifier) must be between 3v and 5,5v. audvdd, hsvdd and vdd must be inferior or equal to audvbat. a typical application is audvbat connected to a battery and audvdd, hsvdd and vdd supplied by regulators. audvbat must be present at the same time or before a udvdd, hsvdd and vdd. audrst must be active low (0) until the voltages are not etablished and reach the proper values. to avoid noise issues, it is recommended to use ceramic decoupling capacitors for each supply closed to the package. the track of the supplies must be optimized to minimize the resistance especially on audvbat where all the current from the power amplifier comes from. note: refer to the application diagram. audio dac start-up sequence in order to minimize any audio output noise during the start-up, the following sequence should be applied. example of power-on: path dac to headset output ? desassert the reset: write 07h at address 10h. ? all precharge and master on: write ffh at address 0ch. ? line out on: write 30h at address 00h. ? delay 500 ms. ? precharge off: write 0ch at address 01h. ? delay 1 ms. ? line out on, dac on: write 3ch at address 00h. example of power-off: path dac to headset output ? dac off: write 30h at address 00h. ? master off: write 00h at address 0ch. ? delay 1 ms. ? all off: write 00h at address 00h apaon apaprech operating mode 0 0 stand-by 0 1 input capacitors precharge 1 0 active mode 1 1 forbidden state apalp power mode 0 low power mode 1 high power mode 41 at83snd2cmp3 7524b?mp3?05/06 example start i2s ?start dclk. ? rstmask=1. ? resfilz=0 and rstz=0. ? resfilz=1 and rstz=1. ? rstmask=0. ? delay 5 ms. ? ondacl=1 and ondacr=1. ? program all dac settings: audio format, gains... example stop i2s: ? dac off: ondacl=0 and ondacr=0. ? stop i2s and dlck. audio pa sequence pa power-on sequence to avoid an audible ?click? at start-up, the input capacitors have to be pre-charged before the power amplifier. pa power-off sequence to avoid an audible ?click? at power-off, the gain should be set to the minimum gain (- 22db) before setting the power amplifier. precharge control the power up of the circuit can be performed independently for several blocks. the sequence flow starts by setting to high the block specific fastcharge control bit and sub- sequently the associated power control bit. once the power control bit is set to high, the fast charging starts. this action begins a user controlled fastcharge cycle. when the fastcharge period is over, the user must reset the associated fastcharge bit and the block is ready for use. if a power control bit is cleared a new power up sequence is needed. the several blocks with independent power control are identified in table 46. the table describes the power on control and fastcharge bits for each block. table 46. precharge and power control note: note that all block can be precharged simultaneously. powered up block power on control bit precharge control bit vref & vcm generator onmstr prcharge (reg 12; bit 1) left line in amplifier onlnil prchargelnil right line in amplifier onlnir prchargelnir left line out amplifier onlnol prchargelnol right line out amplifier onlnor prchargelnor left d-to-a converter ondacl not needed right d-to-a converter ondacr not needed auxiliary input amplifier onauxin prchargeauxin pa driver output onpadrv prchargepadrv 42 at83snd2cmp3 7524b?mp3?05/06 register table 47. pa control register - pa_ctrl (11h)l reset value = 00000000b 76 5 4 3 2 1 0 -apaon apaprec h apalp apagain3 apagain2 apagain1 apagain0 bit number bit mnemonic description 7-not used 6 apaon audio power amplifier on bit 5 apaprech audio power amplifier precharge bit 4 apalp audio power amplifier low power bit 3:0 apagain3:0 audio power amplifier gain 43 at83snd2cmp3 7524b?mp3?05/06 universal serial bus the product implements a usb device controller supporting full speed data transfer. in addition to the default control endpoint 0, it provides 2 other endpoints, which can be configured in control, bulk, interrupt or isochronous modes: ? endpoint 0: 32-byte fifo, default control endpoint ? endpoint 1, 2: 64-byte ping-pong fifo, this allows the firmware to be developed conforming to most usb device classes, for example: ? usb mass storage class bulk-only transport, revision 1.0 - september 31, 1999 ? usb human interface device class, version 1.1 - april 7, 1999 ? usb device firmware upgrade class, revision 1.0 - may 13, 1999 usb mass storage class bulk-only transport within the bulk-only framework, the control endpoint is only used to transport class- specific and standard usb requests for device set-up and configuration. one bulk-out endpoint is used to transport commands and data from the host to the device. one bulk in endpoint is used to transport status and data from the device to the host. the following at83snd2cmp3 configuration adheres to those requirements: ? endpoint 0: 32 bytes, control in-out ? endpoint 1: 64 bytes, bulk-in ? endpoint 2: 64 bytes, bulk-out usb device firmware upgrade (dfu) the usb device firmware update (dfu) protocol can be used to upgrade the on-chip flash memory of the at83snd2cmp3. this allows installing product enhancements and patches to devices that are already in the field. 2 different configurations and descriptor sets are used to support dfu functions. the run-time configuration co-exist with the usual functions of the device, which is usb mass storage for at83snd2cmp3. it is used to initiate dfu from the normal operating mode. the dfu configuration is used to perform the firmware update after device re-configuration and usb reset. it excludes any other function. only the default control pipe (endpoint 0) is used to support dfu services in both configurations. the only possible value for the maxpacketsize in the dfu configuration is 32 bytes, which is the size of the fifo implemented for endpoint 0. 44 at83snd2cmp3 7524b?mp3?05/06 description the usb device controller provides the hardware that the at83snd2cmp3 needs to interface a usb link to a data flow stored in a double port memory. it requires a 48 mhz reference clock provided by the clock controller as detailed in sec- tion "", page 44. this clock is used to generate a 12 mhz full speed bit clock from the received usb differential data flow and to transmit data according to full speed usb device tolerance. clock recovery is done by a digital phase locked loop (dpll) block. the serial interface engine (sie) block performs nrzi encoding and decoding, bit stuff- ing, crc generation and checking, and the serial-parallel data conversion. the universal function interface (ufi) controls the interface between the data flow and the dual port ram, but also the interface with the c51 core itself. figure 30 shows how to connect the at83snd2cmp3 to the usb connector. d+ and d- pins are connected through 2 termination resistors. value of these resistors is detailed in the section ?dc characteristics?. figure 28. usb device controller block diagram figure 29. usb connection usb clock 48 mhz 12 mhz d+ d- dpll sie ufi usb buffer to/from c51 core d+ d- r usb vbus r usb gnd d+ d- vss to p ow e r su pp ly 45 at83snd2cmp3 7524b?mp3?05/06 clock controller the usb controller clock is generated by division of the pll clock. the division factor is given by usbcd1:0 bits in usbclk register. figure 30 shows the usb controller clock generator and its calculation formula. the usb controller clock frequency must always be 48 mhz. figure 30. usb clock generator and symbol usbcd1:0 usbclk 48 mhz usb clock usbclk pllclk usbcd 1 + -------------------------------- = usb clock usb clock symbol pll clock 46 at83snd2cmp3 7524b?mp3?05/06 serial interface engine (sie) the sie performs the following functions: ? nrzi data encoding and decoding. ? bit stuffing and unstuffing. ? crc generation and checking. ? acks and nacks automatic generation. ? token type identifying. ? address checking. ? clock recovery (using dpll). figure 31. sie block diagram 8 start of packet detector clock recover sync detector pid decoder address decoder serial to parallel converter crc5 & crc16 generator/check usb pattern generator parallel to serial converter bit stuffing nrzi converter crc16 generator nrzi ? nrz bit unstuffing packet bit counter end of packet detector usb clock 48 mhz sysclk data in d+ d- (12 mhz) 8 data ou t 47 at83snd2cmp3 7524b?mp3?05/06 function interface unit (ufi) the function interface unit provides the interface between the at83snd2cmp3 and the sie. it manages transactions at the packet level with minimal intervention from the device firmware, which reads and writes the endpoint fifos. figure 33 shows typical usb in and out transactions reporting the split in the hard- ware (ufi) and software (c51) load. figure 32. ufi block diagram figure 33. usb typical transaction load to/from c51 cor e endpoint control c51 side endpoint control usb side endpoint 2 endpoint 1 endpoint 0 usbcon usbint usbien uepint uepien uepnum uepstax usbaddr uepconx uepdatx ueprst ubyctx ufnumh ufnuml asynchronous information transfer control fsm to/from sie 1 2 mhz dpll out transactions: host ufi c51 out data0 (n bytes) ack endpoint fifo read (n bytes) out data1 nack out data1 ack in transactions: host ufi c51 in ack endpoint fifo write in data1 nack c51 interrupt in data1 c51 interrupt endpoint fifo writ e 48 at83snd2cmp3 7524b?mp3?05/06 upstream resume a usb device can be allowed by the host to send an upstream resume for remote wake-up purpose. when the usb controller receives the set_feature request: device_remote_wakeup, the firmware should set to 1 the rmwupe bit in the usbcon register to enable this functionality. rmwupe value should be 0 in the other cases. if the device is in suspen d mode, the usb controller ca n send an upstream resume by clearing first the spint bit in the usbint register and by setting then to 1 the sdrm- wup bit in the usbcon register. the usb controller sets to 1 the uprsm bit in the usbcon register. all clocks must be enabled first. the remote wake is sent only if the usb bus was in suspend state for at least 5ms. when the upstream resume is com- pleted, the uprsm bit is reset to 0 by hardware. the firmware should then clear the sdrmwup bit. figure 34. example of remote wakeup management usb controller init detection of a suspend state spint set rmwupe suspend management enable clocks upstream resume sent uprsm clear spint set sdmwup clear sdrmwup set_feature: device_remote_wakeup need usb resume uprsm = 1 49 at83snd2cmp3 7524b?mp3?05/06 usb interrupt system interrupt system priorities figure 35. usb interrupt control system table 1. priority levels usb interrupt control system as shown in figure 36, many events can produce a usb interrupt: ? txcmpl: transmitted in data. this bit is set by hardware when the host accept a in packet. ? rxoutb0: received out data bank 0. this bit is set by hardware when an out packet is accepted by the endpoint and stored in bank 0. ? rxoutb1: received out data bank 1 (only for ping-pong endpoints). this bit is set by hardware when an out packet is accepted by the endpoint and stored in bank 1. ? rxsetup: received setup. this bit is set by hardware when an setup packet is accepted by the endpoint. ? stlcrc: stalled (only for control, bulk and interrupt endpoints). this bit is set by hardware when a stall handshake has been sent as requested by stallrq, and is reset by hardware when a setup packet is received. ? sofint: start of frame interrupt . this bit is set by hardware when a usb start of frame packet has been received. ? wupcpu: wake-up cpu interrupt. this bit is set by hardware when a usb resume is detected on the usb bus, after a suspend state. ? spint: suspend interrupt. this bit is set by hardware when a usb suspend is detected on the usb bus. eusb ie1.6 ea ie0.7 usb controller iph/l interrupt enable lowest priority interrupts priority enable 00 01 10 11 d+ d- iphusb iplusb usb priority level 0 0 0..................lowest 01 1 10 2 1 1 3..................highest 50 at83snd2cmp3 7524b?mp3?05/06 figure 36. usb interrupt control block diagram txcmp uepstax.0 rxoutb0 uepstax.1 rxsetup uepstax.2 stlcrc uepstax.3 epxie uepien.x epxint uepint.x sofint usbint.3 esofint usbien.3 spint usbint.0 espint usbien.0 eusb ie1.6 endpoint x (x = 0..2) eorint usbint.4 wupcpu usbint.5 ewupcpu usbien.5 rxoutb1 uepstax.6 eeorint usbien.4 nakout uepconx.5 nakin uepconx.4 nakien uepconx.6 51 at83snd2cmp3 7524b?mp3?05/06 multimedia card controller the at83snd2cmp3 implements a multimedia card (mmc) controller. the mmc is used to store mp3 encoded audio files in removable flash memory cards that can be easily plugged or removed from the application. card concept the basic multimedia card concept is based on transferring data via a minimum number of signals. card signals the communication signals are: ? clk: with each cycle of this signal a one bit transfer on the command and data lines is done. the frequency may vary from zero to the maximum clock frequency. ? cmd: is a bi-directional command channel used for card initialization and data transfer commands. the cmd signal has 2 operation modes: open-drain for initialization mode and push-pull for fast command transfer. commands are sent from the multimedia card bus master to the card and responses from the cards to the host. ? dat: is a bi-directional data channel. the dat signal operates in push-pull mode. only one card or the host is driving this signal at a time. card registers within the card interface five registers are defined: ocr, cid, csd, rca and dsr. these can be accessed only by the corresponding commands. the 32-bit operation conditions register (ocr) stores the v dd voltage profile of the card. the register is optional and can be read only. the 128-bit wide cid register carries the card identification information (card id) used during the card identification procedure. the 128-bit wide card-specific data register (csd) provides information on how to access the card contents. the csd defines the data format, error correction type, maxi- mum data access time, data transfer speed, and whether the dsr register can be used. the 16-bit relative card address register (rca) carries the card address assigned by the host during the card identification. this address is used for the addressed host-card communication after the card identification procedure. the 16-bit driver stage register (dsr) can be optionally used to improve the bus per- formance for extended operating conditions (depending on parameters like bus length, transfer rate or number of cards). bus concept the multimedia card bus is designed to connect either solid-state mass-storage mem- ory or i/o-devices in a card format to multimedia applications. the bus implementation allows the coverage of application fields from low-cost systems to systems with a fast data transfer rate. it is a single master bus with a variable number of slaves. the multi- media card bus master is the bus controller and each slave is either a single mass storage card (with possibly different technologies such as rom, otp, flash etc.) or an i/o-card with its own controlling unit (on card) to perform the data transfer. the multimedia card bus also includes power connections to supply the cards. the bus communication uses a special protocol (multimedia card bus protocol) which is applicable for all devices. therefore, the payload data transfer between the host and the cards can be bi-directional. 52 at83snd2cmp3 7524b?mp3?05/06 bus lines the multimedia card bus architecture requires all cards to be connected to the same set of lines. no card has an individual connection to the host or other devices, which reduces the connection costs of the multimedia card system. the bus lines can be divided into three groups: ? power supply: v ss1 and v ss2 , v dd ? used to supply the cards. ? data transfer: mcmd, mdat ? used for bi-directional communication. ? clock: mclk ? used to synchronize data transfer across the bus. bus protocol after a power-on reset, the host must initialize the cards by a special message-based multimedia card bus protocol. each message is represented by one of the following tokens: ? command: a command is a token which starts an operation. a command is transferred serially from the host to the card on the mcmd line. ? response: a response is a token which is sent from an addressed card (or all connected cards) to the host as an answer to a previously received command. it is transferred serially on the mcmd line. ? data: data can be transferred from the card to the host or vice-versa. data is transferred serially on the mdat line. card addressing is implemented using a session address assigned during the initializa- tion phase, by the bus controller to all currently connected cards. individual cards are identified by their cid number. this method requires that every card will have an unique cid number. to ensure uniqueness of cids the cid register contains 24 bits (mid and oid fields) which are defined by the mmca. every card manufacturers is required to apply for an unique mid (and optionally oid) number. multimedia card bus data transfers are composed of these tokens. one data transfer is a bus operation. there are different types of operations. addressed operations always contain a command and a response token. in addition, some operations have a data token, the others transfer their information directly within the command or response structure. in this case no data token is present in an operation. the bits on the mdat and the mcmd lines are transferred synchronous to the host clock. 2 types of data transfer commands are defined: ? sequential commands: these commands initiate a continuous data stream, they are terminated only when a stop command follows on the mcmd line. this mode reduces the command overhead to an absolute minimum. ? block-oriented commands: these commands send a data block succeeded by crc bits. both read and write operations allow either single or multiple block transmission. a multiple block transmission is terminated when a stop command follows on the mcmd line similarly to the stream read. figure 37 through figure 41 show the different types of operations, on these figures, grayed tokens are from host to card(s) while white tokens are from card(s) to host. figure 37. sequential read operation data stream command response mcmd mdat data stop operation data transfer operation command response stop command 53 at83snd2cmp3 7524b?mp3?05/06 figure 38. (multiple) block read operation as shown in figure 39 and figure 40 the data write operation uses a simple busy signal- ling of the write operation duration on the data line (mdat). figure 39. sequential write operation figure 40. multiple block write operation figure 41. no response and no data operation command token format as shown in figure 42, commands have a fixed code length of 48 bits. each command token is preceded by a start bit: a low level on mcmd line and succeeded by an end bit: a high level on mcmd line. the command content is preceded by a transmission bit: a high level on mcmd line for a command token (host to card) and succeeded by a 7 - bit crc so that transmission errors can be detected and the operation may be repeated. command content contains the command index and address information or parameters. figure 42. command token format data block mcmd mdat data stop operation block read operation crc multiple block read operation command response command response data block crc data block crc stop command data stream mcmd mdat data stop operation data transfer operation command response command response stop command busy mcmd mdat data stop operation block write operation multiple block write operation busy data block crc data block crc command response command response stop command status busy status command mcmd mdat no data operation no response operation command response 0 total length = 48 bits content crc 1 1 54 at83snd2cmp3 7524b?mp3?05/06 table 48. command token format response token format there are five types of response tokens (r1 to r5). as shown in figure 43, responses have a code length of 48 bits or 136 bits. a response token is preceded by a start bit: a low level on mcmd line and succeeded by an end bit: a high level on mcmd line. the command content is preceded by a transmission bit: a low level on mcmd line for a response token (card to host) and succeeded (r1,r2,r4,r5) or not (r3) by a 7 - bit crc. response content contains mirrored command and status information (r1 response), cid register or csd register (r2 response), ocr register (r3 response), or rca regis- ter (r4 and r5 response). figure 43. response token format table 49. r1 response format (normal response) table 50. r2 response format (cid and csd registers) bit position 47 46 45:40 39:8 7:1 0 width (bits) 1163271 value ?0? ?1? - - - ?1? description start bit transmission bit command index argument crc7 end bit bit position 47 46 45:40 39:8 7:1 0 width (bits) 1163271 value ?0? ?0? - - - ?1? description start bit transmission bit command index card status crc7 end bit bit position 135 134 [133:128] [127:1] 0 width (bits) 116321 value ?0? ?0? ?111111? - ?1? description start bit transmission bit reserved argument end bit 0 total length = 48 bits content crc 0 1 r1, r4, r5 0 total length = 136 bits content = cid or csd crc 0 1 r2 0 total length = 48 bits content 0 1 r3 55 at83snd2cmp3 7524b?mp3?05/06 table 51. r3 response format (ocr register) table 52. r4 response format (fast i/o) table 53. r5 response format data packet format there are 2 types of data packets: stream and block. as shown in figure 44, stream data packets have an indeterminate length while block packets have a fixed length depending on the block length. each data packet is preceded by a start bit: a low level on mcmd line and succeeded by an end bit: a high level on mcmd line. due to the fact that there is no predefined end in stream packets, crc protection is not included in this case. the crc protection algorithm for block data is a 16-bit ccitt polynomial. figure 44. data token format clock control the mmc bus clock signal can be used by the host to turn the cards into energy saving mode or to control the data flow (to avoid under-run or over-run conditions) on the bus. the host is allowed to lower the clock frequency or shut it down. there are a few restrictions the host must follow: ? the bus frequency can be changed at any time (under the restrictions of maximum data transfer frequency, defined by the cards, and the identification frequency defined by the specification document). ? it is an obvious requirement that the clock must be running for the card to output data or response tokens. after the last multimedia card bus transaction, the host is bit position 47 46 [45:40] [39:8] [7:1] 0 width (bits) 11 63271 value ?0? ?0? ?111111? - ?1111111? ?1? description start bit transmission bit reserved ocr register reserved end bit bit position 47 46 [45:40] [39:8] [7:1] 0 width (bits) 11 63271 value ?0? ?0? ?100111? - - ?1? description start bit transmission bit command index argument crc7 end bit bit position 47 46 [45:40] [39:8] [7:1] 0 width (bits) 11 63271 value ?0? ?0? ?101000? - - ?1? description start bit transmission bit command index argument crc7 end bit 0 content 1 sequential data crc block data 0 content 1 block length 56 at83snd2cmp3 7524b?mp3?05/06 required, to provide 8 (eight) clock cycles for the card to complete the operation before shutting down the clock. following is a list of the various bus transactions: ? a command with no response. 8 cl ocks after the host command end bit. ? a command with response. 8 clo cks after the card command end bit. ? a read data transaction. 8 clocks after the end bit of the last data block. ? a write data transaction. 8 clocks after the crc status token. ? the host is allowed to shut down the clock of a ?busy? card. the card will complete the programming operation regardless of the host clock. however, the host must provide a clock edge for the card to turn off its busy signal. without a clock edge the card (unless previously disconnected by a deselect command-cmd7) will force the mdat line down, forever. description the mmc controller interfaces to the c51 core through the following eight special func- tion registers: mmcon0, mmcon1, mmcon2, the three mmc control registers; mmsta, the mmc status register ; mmint, the mmc interrupt register; mmmsk, the mmc interrupt mask register; mmcmd, the mmc command register; mmdat, the mmc data register; and mmclk, the mmc clock register. as shown in figure 45, the mmc controller is divided in four blocks: the clock generator that handles the mclk (formally the mmc clk) output to the card, the command line controller that handles the mcmd (formally the mmc cmd) line traffic to or from the card, the data line controller that handles the mdat (formally the mmc dat) line traffic to or from the card, and the interrupt controller that handles the mmc controller interrupt sources. these blocks are detailed in the following sections. figure 45. mmc controller block diagram clock generator the mmc clock is generated by division of the oscillator clock (f osc ) issued from the clock controller block as detailed in section "oscillator", page 10. the division factor is given by mmcd7:0 bits in mmclk register, a value of 0x00 stops the mmc clock. figure 46 shows the mmc clock generator and its output clock calculation formula. osc clock mcmd mclk 8 internal bus mdat command line clock mmc interrupt request generator controller data line controller interrupt controller 57 at83snd2cmp3 7524b?mp3?05/06 figure 46. mmc clock generator and symbol as soon as mmcen bit in mmcon2 is set, the mmc controller receives its system clock. the mmc command and data clock is generated on mclk output and sent to the command line and data line controllers. figure 47 shows the mmc controller configura- tion flow. as exposed in section ?clock control?, page 55, mmcd7:0 bits can be used to dynami- cally increase or reduce the mmc clock. figure 47. configuration flow mmcd7:0 mmclk mmc clock mmcclk oscclk mmcd 1 + --------------------------- -- = osc clock mmcen mmcon2.7 controller clock mmc clock mmc clock symbol mmc controller configuration configure mmc clock mmclk = xxh mmcen = 1 flowc = 0 58 at83snd2cmp3 7524b?mp3?05/06 command line controller as shown in figure 48, the command line controller is divided in 2 channels: the com- mand transmitter channel that handles the command transmission to the card through the mcmd line and the command receiver channel that handles the response reception from the card through the mcmd line. these channels are detailed in the following sections. figure 48. command line controller block diagram command transmitter for sending a command to the card, user must load the command index (1 byte) and argument (4 bytes) in the command transmit fifo using the mmcmd register. before starting transmission by setting and clearing the cmden bit in mmcon1 register, user must first configure: ? respen bit in mmcon1 register to indica te whether a response is expect ed or not. ? rfmt bit in mmcon0 register to indicate the response size expected. ? crcdis bit in mmcon0 register to indicate whether the crc7 included in the response will be computed or not. in order to avoid crc error, crcdis may be set for response that do not include crc7. figure 49 summarizes the command transmission flow. as soon as command transmission is enabled, the cflck flag in mmsta is set indicat- ing that write to the fifo is locked. this mechanism is implemented to avoid command overrun. the end of the command transmission is signalled to you by the eoci flag in mmint register becoming set. this flag may generate an mmc interrupt request as detailed in section "interrupt", page 66. the end of the command transmission also resets the cflck flag. ctptr mmcon0.4 crptr mmcon0.5 mcm d cmden mmcon1.0 tx command line finished state machine data converter // -> serial 5-byte fifo mmcmd tx pointer rfmt mmcon0.1 crcdis mmcon0.0 respen mmcon1.1 data converter serial -> // rx pointer 17 - byte fifo mmcmd cflck mmsta.0 crc7 generator rx command line finished state machine crc7 and format checker crc7s mmsta.2 respfs mmsta.1 eoci mmint.5 eori mmint.6 command transmitter command receiver write read 59 at83snd2cmp3 7524b?mp3?05/06 user may abort command loading by setting and clearing the ctptr bit in mmcon0 register which resets the write pointer to the transmit fifo. figure 49. command transmission flow command receiver the end of the response reception is signalled to you by the eori flag in mmint regis- ter. this flag may generate an mmc interrupt request as detailed in section "interrupt", page 66. when this flag is set, 2 other flags in mmsta register: respfs and crc7s give a status on the response received. respfs indicates if the response format is cor- rect or not: the size is the one expected (48 bits or 136 bits) and a valid end bit has been received, and crc7s indicates if the crc7 computation is correct or not. these flags are cleared when a command is sent to the card and updated when the response has been received. user may abort response reading by setting and clearing the crptr bit in mmcon0 register which resets the read pointer to the receive fifo. according to the mmc specification delay between a command and a response (for- mally n cr parameter) can not exceed 64 mmc clock periods. to avoid any locking of the mmc controller when card does not send its response (e.g. physically removed from the bus), user must launch a time-out period to exit from such situation. in case of time- out user may reset the command controller and its internal state machine by setting and clearing the ccr bit in mmcon2 register. this time-out may be disarmed when receiving the response. command transmission load command in buffer mmcmd = index mmcmd = argument configure response respen = x rfmt = x crcdis = x transmit command cmden = 1 cmden = 0 60 at83snd2cmp3 7524b?mp3?05/06 data line controller the data line controller is based on a 16-byte fifo used both by the data transmitter channel and by the data receiver channel. figure 50. data line controller block diagram fifo implementation the 16-byte fifo is based on a dual 8-byte fifos managed using 2 pointers and four flags indicating the status full and empty of each fifo. pointers are not accessible to user but can be reset at any time by setting and clearing drptr and dtptr bits in mmcon0 register. resetting the pointers is equivalent to abort the writing or reading of data. f1ei and f2ei flags in mmint register signal when set that respectively fifo1 and fifo2 are empty. f1fi and f2fi flags in mmint register signal when set that respec- tively fifo1 and fifo2 are full. these flags may generate an mmc interrupt request as detailed in section ?interrupt?. data configuration before sending or receiving any data, the data line controller must be configured accord- ing to the type of the data transfer considered. this is achieved using the data format bit: dfmt in mmcon0 register. clearing dfmt bit enables the data stream format while setting dfmt bit enables the data block format. in data block format, user must also configure the single or multi-block mode by clearing or setting the mblock bit in mmcon0 register and the block length using blen3:0 bits in mmcon1 according to table 54. figure 51 summarizes the data modes configuration flows. table 54. block length programming mcbi mmint.1 datfs mmsta.3 crc16s mmsta.4 f2fi mmint.3 f2ei mmint.1 dfmt mmcon0.2 mblock mmcon0.3 datdir mmcon1.3 data converter // -> serial blen3:0 mmcon1.7:4 daten mmcon1.2 data line finished state machine data converter serial -> // dtptr mmcon0.6 drptr mmcon0.7 tx pointer rx pointer 8-byte fifo 1 8-byte fifo 2 16-byte fifo mmdat f1ei mmint.0 crc16 and format checker f1fi mmint.2 eofi mmint.4 cbusy mmsta.5 crc16 generator mda t blen3:0 block length (byte) blen = 0000 to 1011 length = 2 blen : 1 to 2048 > 1011 reserved: do not program blen3:0 > 1011 61 at83snd2cmp3 7524b?mp3?05/06 figure 51. data controller configuration flows data transmitter configuration for transmitting data to the card user must first configure the data controller in transmis- sion mode by setting the datdir bit in mmcon1 register. figure 52 summarizes the data stream transmission flows in both polling and interrupt modes while figure 53 summarizes the data block transmission flows in both polling and interrupt modes, these flows assume that block length is greater than 16 data. data loading data is loaded in the fifo by writing to mmdat register. number of data loaded may vary from 1 to 16 bytes. then if necessary (more than 16 bytes to send) user must wait that one fifo becomes empty (f1ei or f2ei set) before loading 8 new data. data transmission transmission is enabled by setting and clearing daten bit in mmcon1 register. data is transmitted immediately if the response has already been received, or is delayed after the response reception if its status is correct. in both cases transmission is delayed if a card sends a busy state on the data line until the end of this busy condition. according to the mmc specification, the data transfer from the host to the card may not start sooner than 2 mmc clock periods after the card response was received (formally n wr parameter). to address all card types, this delay can be programmed using datd1:0 bits in mmcon2 register from 3 mmc clock periods when datd1:0 bits are cleared to 9 mmc clock periods when datd1:0 bits are set, by step of 2 mmc clock periods. end of transmission the end of a data frame (block or stream) transmission is signalled to you by the eofi flag in mmint register. this flag may generate an mmc interrupt request as detailed in section "interrupt", page 66. in data stream mode, eofi flag is set, after reception of the end bit. this assumes user has previously sent the stop command to the card, which is the only way to stop stream transfer. in data block mode, eofi flag is set, after reception of the crc status token (see figure 43). 2 other flags in mmsta register: datfs and crc16s report a status on the frame sent. datfs indicates if the crc status token format is correct or not, and crc16s indicates if the card has found the crc16 of the block correct or not. busy status as shown in figure 43 the card uses a busy token during a block write operation. this busy status is reported to you by the cbusy flag in mmsta register and by the mcbi flag in mmint which is set every time cbusy toggles, i.e. when the card enters and exits its busy state. this flag may generate an mmc interrupt request as detailed in sec- tion "interrupt", page 66. data single block configuration data stream configuration configure format dfmt = 0 data multi-block configuration configure format dfmt = 1 mblock = 1 blen3:0 = xxxxb configure format dfmt = 1 mblock = 0 blen3:0 = xxxxb 62 at83snd2cmp3 7524b?mp3?05/06 figure 52. data stream transmission flows send stop command data stream transmission start transmission daten = 1 daten = 0 fifo empty? f1ei or f2ei = 1? fifo filling write 8 data to mmdat no more data to send? fifos filling write 16 data to mmdat a. polling mode data stream initialization fifos filling write 16 data to mmdat data stream transmission isr fifo filling write 8 data to mmdat send stop command no more data to send? b. interrupt mode fifo empty? f1ei or f2ei = 1? start transmission daten = 1 daten = 0 unmask fifos empty f1em = 0 f2em = 0 mask fifos empty f1em = 1 f2em = 1 63 at83snd2cmp3 7524b?mp3?05/06 figure 53. data block transmission flows data receiver configuration to receive data from the card you must first configure the data controller in reception mode by clearing the datdir bit in mmcon1 register. figure 54 summarizes the data stream reception flows in both polling and interrupt modes while figure 55 summarizes the data block reception flows in both polling and interrupt modes, these flows assume that block length is greater than 16 bytes. data reception the end of a data frame (block or stream) reception is signalled to you by the eofi flag in mmint register. this flag may generate an mmc interrupt request as detailed in sec- tion "interrupt", page 66. when this flag is set, 2 other flags in mmsta register: datfs and crc16s give a status on the frame received. datfs indicates if the frame format is correct or not: a valid end bit has been received, and crc16s indicates if the crc16 computation is correct or not. in case of data stream crc16s has no meaning and stays cleared. according to the mmc specification data transmission from the card starts after the access time delay (formally n ac parameter) beginning from the end bit of the read com- mand. to avoid any locking of the mmc controller when card does not send its data (e.g. physically removed from the bus), you must launch a time-out period to exit from such situation. in case of time-out you may reset the data controller and its internal state machine by setting and clearing the dcr bit in mmcon2 register. data block transmission start transmission daten = 1 daten = 0 fifo empty? f1ei or f2ei = 1? fifo filling write 8 data to mmdat no more data to send? fifos filling write 16 data to mmdat a. polling mode data block initialization start transmission daten = 1 daten = 0 fifos filling write 16 data to mmdat data block transmission isr fifo filling write 8 data to mmdat no more data to send? b. interrupt mode fifo empty? f1ei or f2ei = 1? mask fifos empty f1em = 1 f2em = 1 unmask fifos empty f1em = 0 f2em = 0 64 at83snd2cmp3 7524b?mp3?05/06 this time-out may be disarmed after receiving 8 data (f1fi flag set) or after receiving end of frame (eofi flag set) in case of block length less than 8 data (1, 2 or 4). data reading data is read from the fifo by reading to mmdat register. each time one fifo becomes full (f1fi or f2fi set), user is requested to flush this fifo by reading 8 data. figure 54. data stream reception flows data stream reception fifo full? f1fi or f2fi = 1? fifo reading read 8 data from mmdat no more data to receive? a. polling mode data stream initialization data stream reception isr fifo reading read 8 data from mmdat send stop command no more data to receive? b. interrupt mode fifo full? f1fi or f2fi = 1? unmask fifos full f1fm = 0 f2fm = 0 send stop command mask fifos full f1fm = 1 f2fm = 1 65 at83snd2cmp3 7524b?mp3?05/06 figure 55. data block reception flows flow control to allow transfer at high speed without taking care of cpu oscillator frequency, the flowc bit in mmcon2 allows control of the data flow in both transmission and reception. during transmission, setting the flowc bit has the following effects: ? mmclk is stopped when both fifos become empty: f1ei and f2ei set. ? mmclk is restarted when one of the fifos becomes full: f1ei or f2ei cleared. during reception, setting the flowc bit has the following effects: ? mmclk is stopped when both fifos become full: f1fi and f2fi set. ? mmclk is restarted when one of the fifos becomes empty: f1fi or f2fi cleared. as soon as the clock is stopped, the mmc bus is frozen and remains in its state until the clock is restored by writing or reading data in mmdat. data block reception start transmission daten = 1 daten = 0 fifo full? f1ei or f2ei = 1? fifo reading read 8 data from mmdat no more data to receive? a. polling mode data block initialization start transmission daten = 1 daten = 0 data block reception isr fifo reading read 8 data from mmdat no more data to receive? b. interrupt mode fifo full? f1ei or f2ei = 1? mask fifos full f1fm = 1 f2fm = 1 unmask fifos full f1fm = 0 f2fm = 0 66 at83snd2cmp3 7524b?mp3?05/06 interrupt description as shown in figure 56, the mmc controller implements eight interrupt sources reported in mcbi, eori, eoci, eofi, f2fi, f1fi, and f2ei flags in mmcint register. these flags are detailed in the previous sections. all these sources are maskable separately using mcbm, eorm, eocm, eofm, f2fm, f1fm, and f2em mask bits respectively in mmmsk register. the interrupt request is generated each time an unmasked flag is set, and the global mmc controller interrupt enable bit is set (emmc in ien1 register). reading the mmint register automatically clears the interrupt flags (acknowledgment). this implies that register content must be saved and tested interrupt flag by interrupt flag to be sure not to forget any interrupts. figure 56. mmc controller interrupt system mmc interface interrupt reques t mcbi mmint.7 eocm mmmsk.5 emmc ien1.0 mcbm mmmsk.7 eorm mmmsk.6 eofi mmint.4 f2fm mmmsk.3 eofm mmmsk.4 eori mmint.6 f2fi mmint.3 eoci mmint.5 f2em mmmsk.1 f1fm mmmsk.2 f1ei mmint.0 f1em mmmsk.0 f1fi mmint.2 f2ei mmint.1 67 at83snd2cmp3 7524b?mp3?05/06 serial i/o port the serial i/o port in the at83snd2cmp3 provides both synchronous and asynchro- nous communication modes. it operates as a synchronous receiver and transmitter in one single mode (mode 0) and operates as an universal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous modes support framing error detection and multiprocessor communication with auto- matic address recognition. mode selection sm0 and sm1 bits in scon register are used to select a mode among the single syn- chronous and the three asynchronous modes according to table 55. table 55. serial i/o port mode selection baud rate generator depending on the mode and the source selection, the baud rate can be generated from either the timer 1 or the internal baud rate generator. the timer 1 can be used in modes 1 and 3 while the internal baud rate generator can be used in modes 0, 1 and 3. the addition of the internal baud rate generator allows freeing of the timer 1 for other purposes in the application. it is highly recommended to use the internal baud rate generator as it allows higher and more accurate baud rates than timer 1. baud rate formulas depend on the modes selected and are given in the following mode sections. timer 1 when using timer 1, the baud rate is derived from the overflow of the timer. as shown in figure 57 timer 1 is used in its 8-bit auto-reload mode (detailed in section "mode 2 (8-bit timer with auto-reload)", page 53). smod1 bit in pcon register allows doubling of the generated baud rate. figure 57. timer 1 baud rate generator block diagram sm0 sm1 mode description baud rate 0 0 0 synchronous shift register fixed/variable 0 1 1 8-bit uart variable 10 29-bit uart fixed 1 1 3 9-bit uart variable tr1 tcon.6 0 1 gate1 tmod.7 overflow c/t1# tmod.6 tl1 (8 bits) th1 (8 bits) int1 t1 per clock 6 0 1 smod1 pcon.7 2 t1 clock to seri al port 68 at83snd2cmp3 7524b?mp3?05/06 internal baud rate generator when using the internal baud rate generator, the baud rate is derived from the over- flow of the timer. as shown in figure 58 the internal baud rate generator is an 8-bit auto-reload timer fed by the peripheral clock or by the peripheral clock divided by 6 depending on the spd bit in bdrcon register. the internal baud rate generator is enabled by setting bbr bit in bdrcon register. smod1 bit in pcon register allows doubling of the generated baud rate. figure 58. internal baud rate generator block diagram synchronous mode (mode 0) mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the i/0 capabilities of a device with shift registers. the transmit data (txd) pin outputs a set of eight clock pulses while the receive data (rxd) pin transmits or receives a byte of data. the 8-bit data are transmitted and received least-significant bit (lsb) first. shifts occur at a fixed baud rate (see section "baud rate selection (mode 0)", page 69). figure 59 shows the serial port block diagram in mode 0. figure 59. serial i/o port block diagram (mode 0) transmission (mode 0) to start a transmission mode 0, write to scon register clearing bits sm0, sm1. as shown in figure 60, writing the byte to transmit to sbuf register starts the transmis- sion. hardware shifts the lsb (d0) onto the rxd pin during the first clock cycle composed of a high level then low level signal on txd. during the eighth clock cycle the msb (d7) is on the rxd pin. then, hardware drives the rxd pin high and asserts ti to indicate the end of the transmission. 0 1 overflow spd bdrcon.1 brg (8 bits) brl (8 bits) per clock 6 ibrg clock brr bdrcon.4 0 1 smod1 pcon.7 2 to seri al port brg clock tx d rx d sbuf tx sr sbuf rx sr sm1 scon.6 sm0 scon.7 mode decoder m3 m2 m1 m0 mode controller ri scon.0 ti scon.1 per clock baud rate controller 69 at83snd2cmp3 7524b?mp3?05/06 figure 60. transmission waveforms (mode 0) reception (mode 0) to start a reception in mode 0, write to scon register clearing sm0, sm1 and ri bits and setting the ren bit. as shown in figure 61, clock is pulsed and the lsb (d0) is sampled on the rxd pin. the d0 bit is then shifted into the shift register. after eight samplings, the msb (d7) is shifted into the shift register, and hardware asserts ri bit to indicate a completed recep- tion. software can then read the received byte from sbuf register. figure 61. reception waveforms (mode 0) baud rate selection (mode 0) in mode 0, the baud rate can be either, fixed or variable. as shown in figure 62, the selection is done using m0src bit in bdrcon register. figure 63 gives the baud rate calculation formulas for each baud rate source. figure 62. baud rate source selection (mode 0) figure 63. baud rate formulas (mode 0) write to sbuf txd rxd ti d0 d1 d2 d3 d4 d5 d6 d7 write to scon txd rxd ri d0 d1 d2 d3 d4 d5 d6 d7 set ren, clear ri 0 1 m0src bdrcon.0 per clock 6 to serial port ibrg clock baud_rate= 6 (1-spd) ? 32 ? (256 -brl) 2 smod1 ? f per brl= 256 - 6 (1-spd) ? 32 ? baud_rate 2 smod1 ? f per a. fixed formula b. variable formula baud_rate = 6 f per 70 at83snd2cmp3 7524b?mp3?05/06 asynchronous modes (modes 1, 2 and 3) the serial port has one 8-bit and 2 9-bit asynchronous modes of operation. figure 64 shows the serial port block diagram in such asynchronous modes. figure 64. serial i/o port block diagram (modes 1, 2 and 3) mode 1 mode 1 is a full-duplex, asynchronous mode. the data frame (see figure 65) consists of 10 bits: one start, eight data bits and one stop bit. serial data is transmitted on the txd pin and received on the rxd pin. when a data is received, the stop bit is read in the rb8 bit in scon register. figure 65. data frame format (mode 1) modes 2 and 3 modes 2 and 3 are full-duplex, asynchronous modes. the data frame (see figure 66) consists of 11 bits: one start bit, eight data bits (transmitted and received lsb first), one programmable ninth data bit and one stop bit. serial data is transmitted on the txd pin and received on the rxd pin. on receive, the ninth bit is read from rb8 bit in scon register. on transmit, the ninth data bit is written to tb8 bit in scon register. alterna- tively, you can use the ninth bit can be used as a command/data flag. figure 66. data frame format (modes 2 and 3) transmission (modes 1, 2 and 3) to initiate a transmission, write to scon register, set the sm0 and sm1 bits according to table 55, and set the ninth bit by writing to tb8 bit. then, writing the byte to be trans- mitted to sbuf register starts the transmission. reception (modes 1, 2 and 3) to prepare for reception, write to scon register, set the sm0 and sm1 bits according to table 55, and set the ren bit. the actual reception is then initiated by a detected high- to-low transition on the rxd pin. tb8 scon.3 ibrg clock rx d tx d sbuf tx sr rx sr sm1 scon.6 sm0 scon.7 mode decoder m3 m2 m1 m0 ri scon.0 ti scon.1 mode & clock controller sbuf rx rb8 scon.2 sm2 scon.4 t1 clock per clock m ode 1 d0 d1 d2 d3 d4 d5 d6 d7 start bit 8-bit data stop bit d0 d1 d2 d3 d4 d5 d6 d8 start bit 9-bit data stop bit d7 71 at83snd2cmp3 7524b?mp3?05/06 framing error detection (modes 1, 2 and 3) framing error detection is provided for the three asynchronous modes. to enable the framing bit error detection feature, set smod0 bit in pcon register as shown in figure 67. when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by 2 devices. if a valid stop bit is not found, the software sets fe bit in scon register. software may examine fe bit after each reception to check for data errors. once set, only software or a chip reset clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when the framing error detection feature is enabled, ri rises on stop bit instead of the last data bit as detailed in figure 73. figure 67. framing error block diagram baud rate selection (modes 1 and 3) in modes 1 and 3, the baud rate is derived either from the timer 1 or the internal baud rate generator and allows different baud rate in reception and transmission. as shown in figure 68 the selection is done using rbck and tbck bits in bdrcon register. figure 69 gives the baud rate calculation formulas for each baud rate source while table 56 details internal baud rate generator configuration for different peripheral clock frequencies and giving baud rates closer to the standard baud rates. figure 68. baud rate source selection (modes 1 and 3) figure 69. baud rate formulas (modes 1 and 3) sm0 1 0 smod0 pcon.6 sm0/fe scon.7 framing error controller fe 0 1 rbck bdrcon.2 t1 clock to serial ibrg clock rx port 0 1 tbck bdrcon.3 t1 clock to seri al ibrg clock tx port 16 16 baud_rate= 6 (1-spd) ? 32 ? (256 -brl) 2 smod1 ? f per brl= 256 - 6 (1-spd) ? 32 ? baud_rate 2 smod1 ? f per baud_rate= 6 ? 32 ? (256 -th1) 2 smod1 ? f per th1= 256 - 192 ? baud_rate 2 smod1 ? f per a. ibrg formula b. t1 formula 72 at83snd2cmp3 7524b?mp3?05/06 notes: 1. these frequencies are achieved in x1 mode, f per = f osc 2. 2. these frequencies are achieved in x2 mode, f per = f osc . baud rate selection (mode 2) in mode 2, the baud rate can only be programmed to 2 fixed values: 1/16 or 1/32 of the peripheral clock frequency. as shown in figure 70 the selection is done using smod1 bit in pcon register. figure 71 gives the baud rate calculation formula depending on the selection. figure 70. baud rate generator selection (mode 2) table 56. internal baud rate generator value baud rate f per = 6 mhz (1) f per = 8 mhz (1) f per = 10 mhz (1) spd smod1 brl error % spd smod1 brl error % spd smod1 brl error % 115200------------ 57600 - - - - 1 1 247 3.55 1 1 245 1.36 38400 1 1 246 2.34 1 1 243 0.16 1 1 240 1.73 19200 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36 9600 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16 4800 1 1 178 0.16 1 1 152 0.16 1 1 126 0.16 baud rate f per = 12 mhz (2) f per = 16 mhz (2) f per = 20 mhz (2) spd smod1 brl error % spd smod1 brl error % spd smod1 brl error % 115200 - - - - 1 1 247 3.55 1 1 245 1.36 57600 1 1 243 0.16 1 1 239 2.12 1 1 234 1.36 38400 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36 19200 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16 9600 1 1 178 0.16 1 1 152 0.16 1 1 126 0.16 4800 1 1 100 0.16 1 1 48 0.16 1 0 126 0.16 0 1 smod1 pcon.7 per clock 2 16 to serial port 73 at83snd2cmp3 7524b?mp3?05/06 figure 71. baud rate formula (mode 2) multiprocessor communication (modes 2 and 3) modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. to enable this feature, set sm2 bit in scon register. when the multiprocessor communica- tion feature is enabled, the serial port can differentiate between data frames (ninth bit clear) and address frames (ninth bit set). this allows the at83snd2cmp3 to function as a slave processor in an environment where multiple slave processors share a single serial line. when the multiprocessor communication feature is enabled, the receiver ignores frames with the ninth bit clear. the receiver examines frames with the ninth bit set for an address match. if the received address matches the slaves address, the receiver hard- ware sets rb8 and ri bits in scon register, generating an interrupt. the addressed slave?s software then clears sm2 bit in scon register and prepares to receive the data bytes. the other slaves are unaffected by these data bytes because they are waiting to respond to their own addresses. automatic address recognition the automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, the automatic address recognition feature in mode 1 may be enabled. in this configuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the device?s address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broadcast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e, setting sm2 bit in scon register in mode 0 has no effect). given address each device has an individual address that is specified in saddr register; the saden register is a mask byte that contains don?t care bits (defined by zeros) to form the device?s given address. the don?t care bits provide the flexibility to address one or more slaves at a time. the following example illustrates how a giv en address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr = 0101 0110b saden = 1111 1100b given = 0101 01xxb baud_rate= 32 2 smod1 ? f per 74 at83snd2cmp3 7524b?mp3?05/06 the following is an example of how to use given addresses to address different slaves: slave a:saddr = 1111 0001b saden = 1111 1010b given = 1111 0x0xb slave b:saddr = 1111 0011b saden = 1111 1001b given = 1111 0xx1b slave c:saddr = 1111 0011b saden = 1111 1101b given = 1111 00x1b the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a don?t-care bit; for slaves b and c, bit 0 is a 1. to com- municate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 0; for slaves b and c, bit 1 is a don?t care bit. to communicate with slaves a and b, but not slave c, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as don?t-care bits, e.g.: saddr = 0101 0110b saden = 1111 1100b (saddr | saden)=1111 111xb the use of don?t-care bits provides flexib ility in defining the br oadcast address, however in most applications, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a:saddr = 1111 0001b saden = 1111 1010b given = 1111 1x11b, slave b:saddr = 1111 0011b saden = 1111 1001b given = 1111 1x11b, slave c:saddr = 1111 0010b saden = 1111 1101b given = 1111 1111b, for slaves a and b, bit 2 is a don?t care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send the address ffh. to communicate with slaves a and b, but not slave c, the master must send the address fbh. reset address on reset, the saddr and saden registers are initialized to 00h, i.e. the given and broadcast addresses are xxxx xxxxb (all don?t care bits). this ensures that the serial port is backwards compatible with the 80c51 microcontrollers that do not support auto- matic address recognition. 75 at83snd2cmp3 7524b?mp3?05/06 interrupt the serial i/o port handles 2 interrupt sources that are the ?end of reception? (ri in scon) and ?end of transmission? (ti in scon) flags. as shown in figure 72 these flags are combined together to appear as a single interrupt source for the c51 core. flags must be cleared by software when executing the serial interrupt service routine. the serial interrupt is enabled by setting es bit in ien0 register. this assumes interrupts are globally enabled by setting ea bit in ien0 register. depending on the selected mode and weather the framing error detection is enabled or disabled, ri flag is set during the stop bit or during the ninth bit as detailed in figure 73. figure 72. serial i/o interrupt system figure 73. interrupt waveforms es ien0.4 serial i/o interrupt request ti scon.1 ri scon.0 rxd d0d1d2d3d4d5d6d7 start bit 8-bit data stop bit ri smod0 = x fe smod0 = 1 a. mode 1 b. mode 2 and 3 rxd d0d1d2d3d4d5d6 d8 start bit 9-bit data stop bit ri smod0 = 1 fe smod0 = 1 d7 ri smod0 = 0 76 at83snd2cmp3 7524b?mp3?05/06 keyboard interface the at83snd2cmp3 implement a keyboard interface allowing the connection of a key- pad. it is based on one input with programma ble interrupt capabilit y on both high or low level. this input allows exit from idle and power down modes. description the keyboard interfaces with the c51 core through 2 special function registers: kbcon, the keyboard control register; and kbsta, the keyboard control and status register. an interrupt enable bit (ekb in ien1 register) allows global enable or disable of the key- board interrupt (see figure 74). as detailed in figure 75 this keyboard input has the capability to detect a programmable level according to kinl0 bit value in kbcon regis- ter. level detection is then reported in interrupt flag kinf0 in kbsta register. a keyboard interrupt is requested each time this flag is set. this flag can be masked by software using kinm0 bits in kbcon register and is cleared by reading kbsta register. figure 74. keyboard interface block diagram figure 75. keyboard input circuitry power reduction mode kin0 inputs allow exit from idle and power-down modes as detailed in section ?power management?, page 46. to enable this feature, kpde bit in kbsta register must be set to logic 1. due to the asynchronous keypad detection in power down mode (all clocks are stopped), exit may happen on parasitic key press. in this case, no key is detected and software must enter power down again. kin0 keyboard interface interrupt request ekb ien1.4 input circuitry kin0 kinm0 kbcon.0 kinf0 kbsta.0 kinl0 kbcon.4 0 1 77 at83snd2cmp3 7524b?mp3?05/06 electrical characteristics absolute maximum rating dc characteristics digital logic storage temperature ......................................... -65 to +150 c voltage on any other pin to v ss .................................... -0.3 to +4.0 v i ol per i/o pin ................................................................. 5 ma power dissipation ............................................................. 1 w operating conditions ambient temperature under bias........................ -40 to +85 c v dd ......................................................................................................... 2.7 to 3.3v *notice: stressing the device beyond the ?absolute maxi- mum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. table 57. digital dc characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c symbol parameter min typ (1) max units test conditions v il input low voltage -0.5 0.2v dd -0.1 v v ih1 (2) input high voltage (except rst, x1) 0.2v dd +1.1 v dd v v ih2 input high voltage (rst, x1) 0.7v dd v dd +0.5 v v ol1 output low voltage (except p0, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 0.45 v i ol = 1.6 ma v ol2 output low voltage (p0, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 0.45 v i ol = 3.2 ma v oh1 output high voltage (p1, p2, p3, p4 and p5) v dd -0.7 v i oh = -30 a v oh2 output high voltage (p0, p2 address mode, mcmd, mdat, mclk, sclk, dclk, dsel, dout, d+, d-) v dd -0.7 v i oh = -3.2 ma i il logical 0 input current (p1, p2, p3, p4 and p5) -50 av in = 0.45 v i li input leakage current (p0, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 10 a 0.45< v in < v dd i tl logical 1 to 0 transition current (p1, p2, p3, p4 and p5) -650 av in = 2.0 v r rst pull-down resistor 50 90 200 k c io pin capacitance 10 pf t a = 25 c v ret v dd data retention limit 1.8 v i dd 78 at83snd2cmp3 7524b?mp3?05/06 notes: 1. typical values are obtained using v dd = 3 v and t a = 25 c. they are not tested and there is no guarantee on these values. table 58. typical reference design at83snd2cmp3 power consumption i dd, i dl and i pd test conditions figure 76. i dd test condition, active mode i dd at83snd2cmp3 operating current x1 / x2 mode 7/ 11.5 9/ 14.5 10.5 / 18 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz i dl at83snd2cmp3 idle mode current x1 / x2 mode 6.3 / 9.1 7.4 / 11.3 8.5 / 14 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz i pd at83snd2cmp3 power-down mode current 20 500 av ret < v dd < 3.3 v table 57. digital dc characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c symbol parameter min typ (1) max units test conditions player mode i dd test conditions stop 10 ma at83snd2cmp3 at 16 mhz, x2 mode, v dd = 3 v no song playing. this consumption does not include audvbat current. playing 37 ma at83snd2cmp3 at 16 mhz, x2 mode, v dd = 3 v mp3 song with fs= 44.1 khz, at any bit rates (variable bit rate) this consumption does not include audvbat current. rst tst p0 all other pins are unconnected vdd vdd vdd i dd vdd pvdd uvdd audvdd x2 clock signal vss x1 (nc) vss pvss uvss audvss 79 at83snd2cmp3 7524b?mp3?05/06 figure 77. i dl test condition, idle mode figure 78. i pd test condition, power-down mode oscillator & crystal schematic figure 79. crystal connection note: for operation with most standard crystals, no external components are needed on x1 and x2. it may be necessary to add external capacitors on x1 and x2 to ground in spe- cial cases (max 10 pf). x1 and x2 may not be used to drive other circuits. parameters table 59. oscillator & crystal characteristics x2 vdd clock signal rst vss tst x1 p0 (nc) i dl all other pins are unconnected vss vdd vss vdd pvdd uvdd audvdd pvss uvss audvss rst mcmd p0 all other pins are unconnected vss vdd tst mdat vdd i pd vdd pvdd uvdd audvdd x2 vss x1 (nc) vss pvss uvss audvss vss x1 x2 q c1 c2 80 at83snd2cmp3 7524b?mp3?05/06 v dd = 2.7 to 3.3 v, t a = -40 to +85 c phase lock loop schematic figure 80. pll filter connection parameters table 60. pll filter characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c usb connection schematic figure 81. usb connection parameters table 61. usb termination characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c symbol parameter min typ max unit c x1 internal capacitance (x1 - vss) 10 pf c x2 internal capacitance (x2 - vss) 10 pf c l equivalent load capacitance (x1 - x2) 5 pf dl drive level 50 w f crystal frequency 20 mhz rs crystal series resistance 40 cs crystal shunt capacitance 6 pf vss filt r c1 c2 vss symbol parameter min typ max unit r filter resistor 100 c1 filter capacitance 1 10 nf c2 filter capacitance 2 2.2 nf d+ d- vbus gnd d+ d- vss to p ow e r su pp ly r usb r usb symbol parameter min typ max unit r usb usb termination resistor 27 81 at83snd2cmp3 7524b?mp3?05/06 dac and pa electrical specifications pa audvbat = 3.6v, ta = 25c unless otherwise noted. high power mode, 100nf capacitor connected between cbp and audvss, 470nf input capacitors, load = 8 ohms. figure 82. pa specification figure 83. maximum dissipated power versus power supply symbol parameter conditions min typ max unit audvbat supply voltage 3.2 - 5.5 v i dd quiescent current inputs shorted, no load - 6 8 ma i ddstby standby current capacitance - - 2 a v cbp dc reference - audvbat/2 - v vos output differential offset full gain -20 0 20 mv z in input impedance active state 12k 20k 30k w z lfp output load full power mode 6 8 32 w z llp output load low-power mode 100 150 300 w c l capacitive load - - 100 pf psrr power supply rejection ratio 200 ? 2khz differential output -60 -db bw output frequency bandwidth 1khz reference frequency 3db attenuation. 470nf input coupling capacitors 50 - 20000 hz t up output setup time off to on mode. voltage already settled. input capacitors precharged -- 10ms v n output noise max gain, a weighted - 120 500 v rms thd hp output distortion high power mode, v dd = 3.2v, 1khz, pout=100mw, gain=0db -50 -db thd lp output distortion low power mode, vdd = 3.2v , 1khz, vout= 100mvpp, max gain, load 8 ohms in serie with 200 ohms -1 -% g acc overall gain accuracy -2 0 2 db g step gain step accuracy -0.7 0 0.7 db 82 at83snd2cmp3 7524b?mp3?05/06 figure 84. dissipated power vs output power, audvbat = 3.2v dac audvdd , hsvdd = 2.8 v, ta=25c, typical case, unless otherwise noted all noise and distortion specifications are measured in the 20 hz to 0.425xfs and a- weighted filtered. full scale levels scale proportionally with the analog supply voltage. figure 85. audio dac specification 200 250 300 350 400 450 500 550 600 3,2 3,4 3,6 3,8 4 4,2 supply voltage audvbat [v] dissipated power [mw] 8 ohms load 6.5 ohms load 0 50 100 150 200 250 300 350 400 450 500 550 600 0 100 200 300 400 500 600 700 800 output power [mw] dissipated power [mw] 8 ohms load 6.5 ohms load overall min typ max units operating temperature -40 +25 +125 c analog supply voltage ( audvdd, hsvdd )2.72.83.3v 83 at83snd2cmp3 7524b?mp3?05/06 digital supply voltage ( vdd )2.42.83.3v audio amplifier supply ( audvbat )3.2-5.5v digital inputs/outputs resolution 20 bits logic family cmos logic coding 2?s complement analog performance ? dac to line-out/headphone output output level for full scale input (for audvdd, hsvdd = 2.8 v) 1.65 vpp output common mode voltage 0.5x hsvdd v output load resistance (on hsl , hsr ) - headphone load - line load 16 32 10 ohm kohm output load capacitance (on hsl , hsr ) - headphone load - line load 30 30 1000 150 pf pf signal to noise ratio (?1dbfs @ 1khz input and 0db gain) - line and headphone loads 87 92 db total harmonic distortion (?1dbfs @ 1khz input and 0db gain) - line load - headphone load - headphone load (16 ohm) -80 -65 -40 -76 -60 db db db dynamic range (measured with -60 dbfs @ 1khz input, extrapolated to full-scale) - line load - headphone load 88 70 93 74 db db interchannel mismatch 0.1 1 db left-channel to right-channel crosstalk (@ 1khz) -90 -80 db output power level control range -6 - 6 db output power level control step 3 db psrr - 1khz - 20khz 55 50 db db maximum output slope at power up (100 to 220f coupling capacitor) 3v/s analog performance ? line-in/microphone input to line-out/headphone output overall min typ max units 84 at83snd2cmp3 7524b?mp3?05/06 input level for full scale output - 0dbfs level @ audvdd, hsvdd = 2.8 v and 0 db gain @ audvdd, hsvdd = 2.8 v and 20 db gain 1.65 583 0.165 58.3 vpp mvrms vpp mvrms input common mode voltage 0.5x audvd d v input impedance 7 10 kohm signal to noise ratio -1 dbfs @ 1khz input and 0 db gain -21 dbfs @ 1khz input and 20 db gain 81 85 71 db dynamic range (extrapolated to full scale level) -60 dbfs @ 1khz input and 0 db gain -60 dbfs @ 1khz input and 20 db gain 82 86 72 db total harmonic distortion ?1dbfs @ 1khz input and 0 db gain ?1dbfs @ 1khz input and 20 db gain -80 -75 -76 -68 db interchannel mismatch 0.1 1 db left-channel to right-channel crosstalk (@ 1khz) -90 -80 db analog performance ? differential mono input amplifier differential input level for full scale output - 0dbfs level @ audvdd, hsvdd = 2.8 v and 0 db gain 1.65 583 vppdif mvrms input common mode voltage 0.5x audvd d v input impedance 7 10 kohm signal to noise ratio (-1 dbfs @ 1khz input and 0 db gain) 76 80 db total harmonic distortion (?1dbfs @ 1khz input and 0 db gain) -85 -81 db analog performance ? pa driver differential output level for full scale input (for audvdd, hsvdd = 3 v) 3.3 vppdif output common mode voltage 0.5x hsvdd v output load 10 30 kohm pf signal to noise ratio (?1dbfs @ 1khz input and 0db gain) 76 80 db total harmonic distortion (?1dbfs @ 1khz input and 0db gain) -75 -71 db master clock master clock maximum long term jitter 1.5 ns pp overall min typ max units 85 at83snd2cmp3 7524b?mp3?05/06 digital filter performance frequency response (10 hz to 20 khz) +/- 0.1 db deviation from linear phase (10 hz to 20 khz) +/- 0.1 deg passband 0.1 db corner 0.4535 fs stopband 0.5465 fs stopband attenuation 65 db de-emphasis filter performance (for 44.1khz fs) frequency gain margin pass band transition band stop band 0hz to 3180hz 3180hz to 10600hz 10600hz to 20khz -1db logarithm decay -10.45db 1db 1db 1db power performance current consumption from audio analog supply avd d , hsvdd in power on 9.5 ma current consumption from audio analog supply avd d , hsvdd in power down 10 a power on settling time - from full power down to full power up (audvref and audvcm decoupling capacitors charge) - linein amplifier (line-in coupling capacitors charge) - driver amplifier (out driver dc blocking capacitors charge) 500 50 500 ms ms ms overall min typ max units 86 at83snd2cmp3 7524b?mp3?05/06 digital filters transfer function figure 86. channel filter figure 87. de-emphasis filter 10 4 -12 87 at83snd2cmp3 7524b?mp3?05/06 audio dac and pa connection figure 88. dac and pa connection audio dac and pa connection audvref auxp painn vss lphn linel liner hsl hsr esdvss ingnd cbp hpn painp hpp audvbat monon monop auxn vdd audvdd audvcm c4 mono input (-) 3v from ldo 3v from ldo 3.2v to 5.5v battery mono differential input c7 8 ohm loud speaker c11 32 ohm headset or line out c8 c5 c6 c3 32 ohm 32 ohm stereo line input c1 c9 c16 c15 c12 r1 c10 r l mono input (+) hsvdd c17 c18 c19 vss hsvss audvss esdvss audvss audvss audvss audvss audvss audvss vss audvss vss 88 at83snd2cmp3 7524b?mp3?05/06 table 62. dac and pa characteristics symbol parameter typ unit c1 capacitance 470 nf c3 capacitance 470 nf c4 capacitance 470 nf c5 capacitance 100 f c6 capacitance 100 f c7 capacitance 100 nf c8 capacitance 470 nf c9 capacitance 100n f c10 capacitance 10 f c11 capacitance 10 f c12 capacitance 470 nf c15 capacitance 470 nf c16 capacitance 22 f c17 capacitance 100 nf c18 capacitance 100 nf c19 capacitance 100 nf r1 resistor 200 89 at83snd2cmp3 7524b?mp3?05/06 mmc interface definition of symbols table 63. mmc interface timing symbol definitions timings table 64. mmc interface ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c, cl 100pf (10 cards) waveforms figure 89. mmc input-output waveforms signals conditions cclock hhigh d data in l low odata out v valid x no longer valid symbol parameter min max unit t chch clock period 50 ns t chcx clock high time 10 ns t clcx clock low time 10 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t dvch input data valid to clock high 3 ns t chdx input data hold after clock high 3 ns t chox output data hold after clock high 5 ns t ovch output data valid to clock high 5 ns t ivch mclk mdat input t chch t clcx t chcx t chcl t clch mcmd input t chix t ovch mdat output mcmd output t chox 90 at83snd2cmp3 7524b?mp3?05/06 audio interface definition of symbols table 65. audio interface timing symbol definitions timings table 66. audio interface ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c, cl 30pf note: 1. 32-bit format with fs= 48 khz. waveforms figure 90. audio interface waveforms signals conditions cclock hhigh o data out l low s data select v valid x no longer valid symbol parameter min max unit t chch clock period 325.5 (1) ns t chcx clock high time 30 ns t clcx clock low time 30 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t clsv clock low to select valid 10 ns t clov clock low to data valid 10 ns d clk t chch t clcx t chcx t clch t chcl dsel d dat right left t clsv t clov 91 at83snd2cmp3 7524b?mp3?05/06 external clock drive and logic level references definition of symbols table 67. external clock timing symbol definitions timings table 68. external clock ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c waveforms figure 91. external clock waveform figure 92. ac testing input/output waveforms note: 1. during ac testing, all inputs are driven at v dd -0.5 v for a logic 1 and 0.45 v for a logic 0. 2. timing measurements are made on all outputs at v ih min for a logic 1 and v il max for a logic 0. figure 93. float waveforms signals conditions cclock hhigh llow x no longer valid symbol parameter min max unit t clcl clock period 50 ns t chcx high time 10 ns t clcx low time 10 ns t clch rise time 3 ns t chcl fall time 3 ns t cr cyclic ratio in x2 mode 40 60 % 0.45 v t clcl v dd - 0.5 v ih1 v il t chcx t clch t chcl t clcx 0.45 v v dd - 0.5 0.7 v dd 0.3 v dd v ih min v il max inputs outputs v load v oh - 0.1 v v ol + 0.1 v v load + 0.1 v v load - 0.1 v timing reference points 92 at83snd2cmp3 7524b?mp3?05/06 note: for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol /i oh = 20 ma. 93 at83snd2cmp3 7524b?mp3?05/06 ordering information part number supply voltage temperature range max frequency package packing product marking rohs compliant at83snd2mp3-7ftil 3v industrial 40 mhz bga100 tray 83c51snd2c-il yes at83snd2mp3-7ftjl 3v industrial & rohs 40 mhz bga100 tray 83c51snd2c-jl yes at83snd2cdvx-7ftil 3v industrial 40 mhz bga100 tray 83c51snd2c-il yes at83snd2cdvx-7ftjl 3v industrial & rohs 40 mhz bga100 tray 83c51snd2c-jl yes 94 at83snd2cmp3 7524b?mp3?05/06 package information ctbga100 document revision history changes from 7524a- 07/05 to 7524b-05/06 1. added at83snd2cdvx part number. table of contents 95 features ................................................................................................. 1 typical applications ............................................................................. 1 description ............................................................................................ 2 block diagram....................................................................................... 3 pin description ...................................................................................... 4 pinouts ................................................................................................................. 4 signals................................................................................................................... 5 internal pin structure............................................................................................ 9 clock controller .................................................................................. 10 oscillator ............................................................................................................ 10 pll ..................................................................................................................... 10 mp3 decoder ....................................................................................... 12 decoder.............................................................................................................. 12 audio controls..................................................................................................... 14 frame information ............................................................................................... 15 ancillary data ..................................................................................................... 15 audio output interface ....................................................................... 16 description ......................................................................................................... 16 clock generator .................................................................................................. 17 data converter ................................................................................................... 17 audio buffer........................................................................................................ 18 mp3 buffer ......................................................................................................... 19 interrupt request................................................................................................ 19 mp3 song playing.............................................................................................. 19 dac and pa interface ......................................................................... 21 dac.................................................................................................................... 21 power amplifier ................................................................................................... 39 audio supplies and start-up............................................................................... 40 universal serial bus ........................................................................... 43 description .......................................................................................................... 44 usb interrupt system......................................................................................... 49 multimedia card controller ................................................................ 51 96 7524b?mp3?05/06 at83snd2cmp3 card concept...................................................................................................... 51 bus concept ....................................................................................................... 51 description.......................................................................................................... 56 clock generator.................................................................................................. 56 command line controller................................................................................... 58 data line controller.............................................................................................60 interrupt ...............................................................................................................66 serial i/o port ...................................................................................... 67 mode selection................................................................................................... 67 baud rate generator.......................................................................................... 67 synchronous mode (mode 0) ............................................................................. 68 asynchronous modes (modes 1, 2 and 3) ...........................................................70 multiprocessor communication (modes 2 and 3) ............................................... 73 automatic address recognition.......................................................................... 73 interrupt ...............................................................................................................75 keyboard interface ............................................................................. 76 description.......................................................................................................... 76 electrical characteristics ................................................................... 77 absolute maximum rating.................................................................................. 77 dc characteristics.............................................................................................. 77 ordering information .......................................................................... 93 package information .......................................................................... 94 ctbga100 ......................................................................................................... 94 document revision history ............................................................... 94 changes from 7524a-07/05 to 7524b-05/06...................................................... 94 printed on recycled paper. 7524b?mp3?05/06 ? atmel corporation 2005 . all rights reserved. atmel ? , logo and combinations thereof, are registered trademarks, and everywhere you are ? are the trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 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